The CPU cache (Cache Memory) is a temporary memory located between the CPU and the memory. Its capacity is much smaller than the memory but the exchange speed is much faster than the memory. The emergence of cache is mainly to solve the contradiction between the CPU operation speed and the memory read and write speed. Because the CPU operation speed is much faster than the memory read and write speed, this will cause the CPU to spend a long time waiting for data to arrive or write data. Memory. The data in the cache is a small part of the memory, but this small part is about to be accessed by the CPU in a short period of time. When the CPU calls a large amount of data, it can be called in the cache first, thereby speeding up the reading speed.
There are three types of CPU caches, the first-level cache (although the first-level cache is the fastest, it has the smallest capacity, and the unit is KB. There is no difference in the first-level cache between different CPUs, so it is not mentioned much now), the second-level cache (the second-level cache) The cache capacity is not large, basically single-digit MB. Except for some server CPUs that have more than 10 MB, CPUs now don’t mention the second-level cache) and the third-level cache. . The L3 cache of common CPUs is only about 10MB (now the AMD EPYC X series has reached 768MB of L3 cache). L3 read and write speeds are much faster than memory. The cache in the CPU is to speed up the CPU to read data and also to give the memory a buffer period. Because the CPU operation speed is too fast, memory reading and writing alone cannot keep up, and the data exchange in the CPU cache is much faster than the memory. Most of the time, the CPU can read the data directly from the cache, and if it cannot find it, read it from the memory. fetch, this can save the time wasted when the CPU reads memory data. When the CPU reads the cache, it will start from the first-level cache, then the second-level cache. When reading the second-level cache, there will sometimes be data misses. At this time, it needs to read from the third-level cache.
Reference link: https://zhuanlan.zhihu.com/p/558199980