Preface
The summary of written test questions is to summarize the problems that may be encountered in the autumn recruitment. Solving the questions is not the purpose. The purpose is to discover your own loopholes in the process of doing the questions and consolidate the foundation.
All question results and explanations are given by the author. The answers are highly subjective. If there are any errors, please point them out in the comment area. The information is compiled from digital IC-related public accounts such as "Digital IC Workers", real questions from websites such as Niuke.com, and online written tests. Transcripts of real questions and interviews.
Keep updated (2023.9.25) The article contains 270 single-choice questions, 106 multiple-choice questions, 16 fill-in-the-blank questions, 17 true-false questions, 72 short-answer questions, 3 logical reasoning questions, and 8 C language python script programming questions Tao .
All the codes provided by the author in this article are written as APIs and can be directly copied to the software to compile, run, and give results.
There are many questions, and even with previous analysis and the powerful ChatGPT, mistakes are inevitable. If you find any mistakes, please feel free to discuss them in the comment area.
In addition, there is a little personal stuff~: At this moment, I feel that I must give...
The total number of words in the solution to the Thousand Questions of the Digital IC Written Test has reached 150,000+, and the webpage is severely stuck in coding, so it is divided into multiple parts to facilitate maintenance. The link is as follows: Solution to the Thousand Questions in the Digital IC Written Test--Single Choice Questions (1)
Digital
IC Solutions to Thousands of Questions in the Written Test - Single-Choice Questions (Part 2) Solutions to
Thousands of Questions in the Digital IC Written Test - Multiple-Choice Questions (Part 3) Solutions to Thousands of Questions
in the Digital IC Written Test - Fill-in-the-Blank Questions (Part 4) )
Solutions to thousands of questions in the digital IC written test - judgment questions (5) Solutions to
thousands of questions in the digital IC written test - short answer questions (6)
Solutions to thousands of questions in the digital IC written test - logical reasoning (7
) Solutions to Thousand Questions of the Digital
Fill in the blanks
-
In verilog, a=4'b10x1;b=4'b10x1; then the logical expression a==b is _______ a===b is ________
Answer: x,1
Equality operator (==): The two operands participating in the comparison must be equal bit by bit, and the result of the equality comparison is 1. If some bits are in an undefined state or have a high resistance value, the result of the equality comparison is undefined. value.
Congruence operator (===): Congruence comparison also compares these uncertain or high-resistance bits. The two operands must be exactly the same, and the result is 1, otherwise the result is 0
For logical operators, please refer to the author’s other articles: Verilog logical AND (&&), bitwise AND (&), logical OR (||), bitwise OR (|), equal (==), congruent (===) The difference
2. The internal calculation of the output signal of the multiplier with 4-bit signal input and 8-bit signal input requires at least ______ bit width
Answer: The maximum value of the 4-bit signal is 4'b1111 = 15, and the maximum value of the 8-bit signal is 8'b1111 1111 = 255;
The maximum value of the product output is: 255 * 15 = (2^4 - 1) * (2^8 - 1) = 2^12 - 2^8 -2^4 + 1, which requires at least 12 bits width.
Change the question: What is the minimum bit width required for the multiplier output of 3-bit signal input and 4-bit signal input?
max_output = 3'b111 * 4'b1111 = 7 * 15 = (2^3 - 1) * (2^4 - 1) = 2^7-2^4-2^3+1, which can be described with 7 bits. It is concluded that the output signal of the multiplier with X bit signal input and Y bit signal input requires at least (X+Y) bit.
3. Under normal circumstances, the chip's operating temperature is _________, the operating voltage is _________, and the speed is the fastest.
Answer: The electron mobility is mainly affected by lattice scattering, that is, the mobility decreases as the temperature increases . The lower the chip operating temperature, the faster the speed. The chip supply voltage affects the charging and discharging speed of the capacitor. When the voltage decreases, the chip will slow down, and when the voltage increases, the chip will become faster.
4.The printout of the following code is___________
always@(posedge clk) begin
a=0;
a<=1;
$display(“%0b”,a);
end
Answer: 0, blocking assignment and non-blocking assignment occur at the same time, the result of blocking assignment shall prevail.
5. All combinational logic is used to implement the operations of A, B, and C |A*(B+C)|^2. A total of _______ multipliers and _______ adders are required.
Answer: 6 multipliers, 5 adders
This question: Suppose A = Ar + Ai*j, B = Br + Bi*j, C = Cr + Ci*j,
A*(B+C) = (Ar*(Br+Cr) - Ai*(Bi+Ci)) + (Ai*(Br+Cr) + Ar(Bi + Ci))*j,fromBr+Cr = Dr, Bi+Ci = The;
Then, what is required is the square of the modulus of the complex number, |A*(B+C)|^2 = square of the real part + square of the imaginary part = ( Ar*(Br+Cr) - Ai*(Bi+Ci)) ^ 2 + (Ai*(Br+Cr) + Ar(Bi + Ci)) ^ 2
= Ar ^ 2 * (Dr ^ 2 + Di ^ 2) + Ai ^ 2 * (Di^2 + Dr^2), whereas Br+Cr = Dr, Bi+Ci = Di;
Multiplier used: Ar*Ar;Ai*Ai;Dr*Dr;Di*Di;Ar ^ 2 * (Dr ^ 2 + Di ^ 2);Ai ^ 2 * (Di^2 + Dr^2); 6 Multiplier
Adder used: Br+Cr;Bi+Ci; Di^2 + Dr^2;Ar ^ 2 * (Dr ^ 2 + Di ^ 2) + Ai ^ 2 * (Di^2 + Dr^2); 4 Adder
6. [Python] list1 = [0, 1, 2, 3, 4, 5], then list1[ : -2]=___
Answer: [0,1,2,3]. Examine python syntax.
7.Which function is used to exit the simulation?
Answer: $finish.
8. Which phase in UVM is the bottom-up execution order? ____
Answer: build_phase
In UVM, build_phase is the phase executed from bottom to top and is also the first phase executed in UVM. build_phase is used to create and connect test components. Its execution order is related to the inheritance relationship of components in testbench. It is generally executed from bottom to top, that is, the lowest-level component is created and connected first, and then other components are created and connected upwards. In build_phase , we can use various factories and configuration mechanisms provided by UVM to dynamically create and configure test components to meet test requirements.
9. The accuracy of a certain digital-to-analog converter is 6 bits, and the voltage conversion range is 0-6.3V. Then when the input digital signal is 011011, the output voltage is ( ) V
Answer: 2'b011011 converted to decimal equals 16+8+2+1=27, which is 2.7V.
10. When performing 256-point FFT analysis, if the signal sampling rate is 4096Hz, then the spectrum resolution after FFT transformation is ( ) Hz.
Answer: 4096/256=16, resolution is 16Hz.
11. The following verilog code implements ( ) frequency division (note: fill in Arabic numerals)
module div(
input clk ,
input rst ,
output clk_ out
);
reg [1:0]cnt1;
reg [1:0]cnt2;
reg c1k1;
reg clk2;
always@(posedge clk or negedge rst_n)
if(!rst_n)
begin cnt1<=2' b00;
else if(cnt1==2'b10)
cnt1<=2'b00;
else
cnt1<=cnt1+1'b1;
always@(negedge clk or negedge rst_n)
if(!rst_n)
cnt2<=2 'b00;
else if(cnt2==2'b10)
cnt2<=2'b00;
else
cnt2<=cnt2+1'b1;
always@(posedge clk or negedge rst_n)
if(!rst_ n)
c1k1<=1'b0;
else if(cnt1==2'b00||cnt1==2'b10)
clk1=~clk1;
else
clk1<=clk1;
always@(negedge clk or negedge rst_n)
if(!rst_ n)
clk2<=1'b0;
else if(cnt2==2'b00||cnt2==2'b10)
clk2<=~clk2;
else
clk2<=clk2;
assign clk_out=clk1&clk2;
endmoduleAnswer: clk1 and clk2 are both three-way frequency with a duty cycle of 66%, clk2 is offset by half a cycle of clk1, and their phase and output are three-way frequency with a duty cycle of 50%.
12. Consider the computer instructions shown below:
Loop:
fld f0,0(x1)
fadd.d f4,f0,f2
fsd f4,0(x1)
addi x1,x1,-8
bne x1, x2, LoopIt is known that the fld instruction takes 2T of time, fadd.d takes 3T of time, and fsd, addi, and bne take 1T of time. Then through the rearrangement of instructions, the minimum time required to complete the above single Loop is ( ) T
Answer:
-
fld f0,0(x1) : Read a double-precision floating-point number from the memory with x1 as the base address and offset 0 (that is, the position pointed to by x1), and store it in the floating-point register f0.
-
fadd.d f4,f0,f2 : Add the value in the f0 register to the value in the f2 register, and store the result in the f4 register.
-
fsd f4,8(x1) : Store the value in the f4 register into a memory location with x1 as the base address and offset 8.
-
addi x1,x1,-8 : Subtract 8 from the value in the x1 register, that is, point the x1 register to the memory address of the previous double-precision floating point number.
-
bne x1,x2, Loop : Compare the value of x1 register with the value of x2 register. If they are not equal, jump to the Loop label for execution.
Observing the instructions, we can find that the fld instruction needs to wait for memory access, the fadd.d instruction needs to wait for the result of the fld instruction, and the fsd instruction also needs to wait for the result of the fadd.d instruction. Therefore, instruction rearrangement can be used to reduce the total execution time.
One possible way to rearrange the instructions is as follows:
Loop:
fld f0,0(x1)
addi x1,x1,-8
fadd.d f4,f0,f2
fsd f4,8(x1)
bne x1,x2,LoopAfter the instructions are rearranged, the fld instruction and the addi instruction can be executed in parallel. The fadd.d instruction waits for the result of the fld instruction, and the fsd instruction waits for the result of the fadd.d instruction. Therefore, the minimum time required for a single Loop is:
2T (fld and addi are executed in parallel) + 3T (fadd.d is executed) + 1T (fsd is executed) + 1T (bne is executed) = 7T
Therefore, the minimum time required to complete the above single Loop is 7T.
13. It is known that VIL_max is the maximum allowable input low level, VIH_min is the minimum allowable input high level, VOL_max is the maximum output low level, and VOH_min is the minimum output high level, then the noise margin of the input high level is VNH= ( )V
Circuit type Supply voltage VIL_max VIH_min VOL_max VOH_min
CMOS 3.3V 1.1V 2.2V 0.1V 3.2V
Answer: 1V, as shown below:
14. In the circuit below, the setup time slack of flip-flop 2 = ( ) ns. (Note: fill in Arabic numerals)
Answer: 0.3+0.65+0.35+T_slack = 0.5+10-0.35. Calculate T_slack=8.85ns.
15. For a certain asynchronous FIFO, the write clock frequency is 200MHz, 30 data will be written every 100 cycles, the read clock frequency is 100MHz, and 7 data can be read every 10 cycles, then the minimum depth of this FIFO is ( ) .(Note: fill in Arabic numerals)
Answer: Easy to figure out, reading speed is faster than writing speed, so the FIFO will not overflow. The 30 pieces of data written account for 30 cycles of the write clock, corresponding to 15 cycles of the read clock. At least 9 data are read out in 15 cycles of the read clock, so the minimum FIFO depth is 21.
The following system verilog code executed ( ) times of printing at 55ns (note: fill in Arabic numerals)
initial begin
$display("start");
#10 $display("test");
fork
$display("test");
#50 $display("test");
#10 $display("test");
begin
#30 $display("test");
#10 $display("test");
end
join_any
$display("test");
#80 $display("test");
endAnswer: 7 prints.
1. The fork-join statement will wait for all subroutines to be executed before continuing to execute subsequent code. The join statement will not return until all subroutines have completed .
2. The fork-join_any statement will wait for at least one subroutine to complete execution before continuing to execute subsequent code. When a subroutine completes, the join statement returns.
3. The fork-join_none statement does not wait for the subroutine to complete execution, but directly continues to execute subsequent code. This kind of statement is often used in situations where there is no need to wait for the subroutine to complete execution.
16.The printed value of the following verilog code is ( )
reg signed [7:0] a, b, c;
initial begin
a=8'h14;
b=8'b11110010;
c=a+b;
$display("%d",c);
endAnswer: 6. b=8'b11110010, the signed bit is two's complement representation, bitwise inversion and 1 are added to obtain b=-14. a=20, so 20-14=6.
17. Given the octal number: (362) 8, find its
The decimal number is:
The original binary code is:
The inverse code is:
The complement is:
Decimal number: 3*8^2+6*8+2=192+48+2=242
The original binary code is: 242 divided by 2 to find the remainder.
242/2=121...0
121/2=60 ...1
60 /2=30 ...0
30 /2=15 ...0
15 /2=7 ...1
7 /2=3 ...1
3 /2=1 ...1
1 /2=0 ...1
Written from bottom to top, the original binary code is: 11110010(B)
The inverse code is: 00001101
The complement is: 00001110
18. Write the output logic expression of the CMOS circuit in the figure: Z1= , Z2=
Left picture: Without looking at B, it is easy to see that A1 and A2 form a NOR gate. If both are 0 at the same time, 1 is output. The pull-up networks of A1 and A2 are connected in parallel with B, and the pull-down networks of A1 and A2 are connected in series with B. So in the end, the NOR of A1 and A2 is combined with the NOR of B, Z1=(B(A1+A2)')'=A1+A2+B'.
Right picture: ABC NOR is connected to a NOT gate, which is the OR of ABC, Z2=A+B+C.
19.Assuming a=1'b1; b=1'b0what's the final values of a and b?
| ① always@(posedge clk) begin a=b; b=a; end |
② always@(posedge clk) a=b; always@(posedge clk) b=a; |
③ always@(posedge clk) begin a<=b; b<=a; end |
④ always@(posedge clk) a<=b; always@(posedge clk) b<=a; |
| a= ? b= ? |
a= ? b= ? |
a= ? b= ? |
a= ? b= ? |
1: Blocking assignment, a=0, b=0.
2: The simulation results are a=0, b=0.
3: Non-blocking assignment: a=0, b=1.
4: Non-blocking assignment: a=0, b=1.
20.Complete the blanks inthe following question with the appropriate answer.
There is a FIFO, at the input side, there will be atmost 80 valid input out of 100 cycles; at the output side there will be atleast 8 available slots out of 10 cycles, please specify what is the minimized FIFOdepth for this case. Depth=_________
Answer: 34. There will be at most 80 valid data in 100 cycles of writing data, and at least 8 valid data in 10 cycles of reading data, which means that the FIFO will not overflow in the worst case. Assume that the input back-to-back transfer writes 160 data in a row. 3 are read in the first five cycles of output, 3 are read in the last five cycles , and 15*8=120 are read in the middle 150 cycles, so 80 data are written, 6+120=126 are read, and the FIFO depth is 160-126=34 . It is easy to misjudge the 32 depth.
21. Logic simplification: Y=B+(~A)&(~C) + (~B)&(~C)
Y=B+A'C'+B'C'=B(1+C')+B'C'+A'C'=B+C'+A'C'=B+C'
Y=B+C'
22. The picture below is the truth table of combinational logic Y=F(A,B,C,D). Please write the corresponding logical expression according to the truth table.
| AB=00 |
AB=01 |
AB=11 |
AB=10 |
|
| CD=00 |
0 |
0 |
0 |
0 |
| CD=01 |
1 |
1 |
1 |
1 |
| CD=11 |
0 |
0 |
1 |
1 |
| CD=10 |
0 |
0 |
1 |
1 |
Simplify the Karnaugh map and write the expression directly: Y=C'D+AD+AC.
23.The initial value of the reg type is ____
Answer: x type.
24.The initial value of wire type is____
Answer: z type.
25. 4'b110x + 4'b0101 = ____
Answer: 4'bxxxx
26. 0xBE & ~0xFC << 0x02 | 0x01= ___________, where:
0xBE = 8'b1011_1110；0xFC = 8'b1111_1100；0x02 = 8'b0000_0010；
Answer: 8'b0000_1101
Negation~The highest priority, priority: Negation operation>Shift operation>Bitwise AND operation>Bitwise OR operation
So the result is:
0xBE & ~0xFC << 0x02 | 0x01
= 8'b1011_1110 & ~8'b1111_1100 << 8'b0000_0010 | 8'b0000_0001
= 8'b1011_1110 & 8'b0000_0011 << 8'b0000_0010 | 8'b0000_0001
= 8'b1011_1110 & 8'b0000_1100 | 8'b0000_0001
= 8'b0000_1100 | 8'b0000_0001
= 8'b0000_1101
