8086 microprocessor is also known as x86, pioneered the X86 architecture era, but also the achievements of Intel, AMD, Microsoft and other international companies.
Brief introduction
Introduction History
April 1972 by Hoff and Fagin developed the world's first 8-bit microprocessor Intel 8008 (8) chip available. 13.8 mm2 in the central processor chip makes 45 kinds of instructions can be executed, it simultaneously eight binary digits and transfer operations.
August 1973, Hoff and others have also developed the Intel 8080 microprocessors, computing speed than its 4004 model to 20 times faster. Development of type 8080 chip was originally just to improve on the 8008 chip, but it was faster new MOS metal oxide semiconductor circuit appeared, Hoff and Fagin the MOS circuit applied to the 8080-type chip, successful, becoming the first second-generation microprocessor, which microprocessor is one of the most successful ever.
Under 8080 (8) of the costumes, which is Jin: integrated 6000 transistors, almost three times that of 4004, 290,000 operations per second, with eight 16-bit address bus and a data bus, contains seven eight bit registers, 16-bit memory, but it also contains a number of input and output ports, and this is a very successful design, an effective solution to the external device in the memory addressing the lack of capacity.
Compared with the first microprocessor, the degree of integration increased from 1 to 4 times, the operation speed increased nearly 20-fold, command system is relatively complete, has a typical computer architecture and interrupt, direct memory access and other functions.
Mol / pendulum Law
1 theory, Moore's Law, it sounds like it should be called a "mole" who put forward. Moore, the name sounds somewhat familiar, yes, this is Moore Gordon Moore, one of Intel co-founder.
1965 Gordon Moore in the magazine "Electronics" (Electronics Magazine) published on page 114 of the impact of science and technology industry since Moore's Law:
- 1, the number of circuits on an integrated circuit chip integrated, doubles every 18 months.
- 2, the performance of microprocessors doubles every 18 months, while prices fell one-half.
- 3, computer performance can buy one US dollar, quadruple every 18 months.
2, with the famous Moore's Law, as well as the famous Intel pendulum strategy:
- In odd years, Intel will introduce new process; (process technology: chip manufacturing process after 1995, from 500 nm, 350 nm, 250 nm, 180 nm, 150 nm, 130 nm, 90 nm, 65 nm, 45 nm, 32 nm, 28 nm, 22 nm, 14 nm, 10 nm, 7 nm, has been developed to future 5 nm.)
- In even-numbered years, Intel will launch a new architecture (processor architecture: CPU manufacturers is to belong to the same series of CPU of a given product specification, the purpose is to distinguish between different types of common CPU important product labeling .Intel series CPU architecture has Socket 423, Socket 478, Socket 775, Socket1366, Socket1156, Socket1155, Socket1150 and Socket2011).
Intel pendulum policy Tick-Tock (in process - in architecture) is a strategic technology development mode of Intel's chips. In this way on two core architecture and manufacturing process to enhance the road, always alternating, on the one hand to avoid the risk of failure while innovation may bring, while sustainable development can reduce development cycles, and can cause persistent market stimulation, and ultimately enhance the competitiveness of their products. Tick refers to the odd-numbered years every two years to launch smaller, more advanced technology processor; Tock refers to processor even-numbered years every two years the introduction of the new architecture.
X86
x86 architecture introduced in 1978 and Intel 8086 central processor first appeared, it is the computer language instruction set executed by a microprocessor, Intel acronym refers to a standard number of general-purpose computer series, also identifies a common set of computer instruction set. Simply put, x86 Intel launched by a complex set of instructions for running the control chip.
x86 History
In 1971, a Japanese calculator manufacturer Intel is the first piece of processors manufactured on Intel's history --4-bit 4004. Soon, in 1975, Intel has introduced eight processors 8008 and 8080.
3 years later, 16 of 8086 debut. In the early 1980s, IBM chose the 8086 derivatives 8088 as the IBM PC processors.
Intel x86 or 80x86 is the first Intel microprocessor architecture to develop a manufacturing Pan said. The series name is based on the earlier processor numbers to represent, and "86" as the end, including Intel 8086,80186,80286,80386 and 80486, so the architecture is called "x86". Since the numbers do not as a registered trademark, so Intel and its competitors are using the name can be registered in the new generation of processors, such as Pentium. X86-32 now called the Intel IA-32, full name "Intel Architecture, 32-bit".
"X86" is a set of machine instructions Intel processors and several other companies set supported, which is generally determined using a standardized chip. From 8086 to 80186,80286,80386,80486, then later Pentium series and now multi-core technology, the use of the x86 instruction set are the same strain, both expanding and backward compatibility.
8086
FIG microcomputer structure
8086 is a 16-bit microprocessor, 16-bit data lines, 20 address lines, 20 bytes of addressing 2 ^ = 1MB
use of 16-bit address bus to I / O port address, a 64K addressable I / O ports;
Interrupt powerful, it can deal with internal and external software interrupt, the interrupt source up to 256;
The internal logical structure of the CPU
1, a bus interface unit (the BIU)
A memory bus interface means responsible for the input and output data transfer ports.
component:
- Of dedicated registers
segment address register (CS, DS, ES, SS, and instruction pointer register are 16-bit IP) - Address adder
8086 in the address space of 1M byte address is a 20-bit address, the address adder adding two 16-bit address to a 20 bit address (segment address left 4 + 16 = 20-bit IP address bit physical address) - 6 byte instruction queue
bus interface unit to fetch from the instruction memory in a buffer, the buffer is called an instruction queue, the execution unit executing the instruction fetch instructions from the instruction execution queue - Input and output control circuit
only way to connect the inner sheet 8086CPU bus to the system bus, it is to exchange data with an external 8086CPU
2, execution section element (EU)
Execution unit is responsible for executing instructions, instructions awaiting execution is usually made from the instruction queue
component:
- The ALU
complete various arithmetic - Flag register FR
some features to save the ALU result information - General register set
data register (AX, BX, CX, DX ), a register (BP, SP, SI, DI are 16-bit) - Execution unit control circuit
3, register set
FIG register 8086 is
BIU and EU can work in parallel, to improve CPU efficiency
. 1, BIU monitoring instruction queue in the instruction queue when there are two null bytes, to automatically queue the instruction fetch
when 2, EU executes the instructions from the instruction queue head instruction fetch unit, and then executed to access memory, the EU issued a request to the BIU, the memory access by the BIU
3, when branch, call, return instruction, the instruction queue changes need to wait for a new load instruction queue , EU it continues executing instructions
CPU external structure
8086 / 8088CPU chips are 40-pin dual in-line package, part of the pin by way of time division multiplexing
8086 / 8088CPU may have two modes of operation: maximum mode and a minimum mode
1, the minimum mode
For small systems constituted by a single microprocessor 8086. In this manner, all of the control signal generating system needs less directly by 8086CPU. System features are: a bus control logic generates and directly controlled by 8086CPU. Other than the CPU module if the acquisition of a bus, the CPU can request, and allows the CPU in response to the module in order to gain control of the bus, after use, in turn returns control to the CPU bus.
2, the maximum mode
For implementing a multiprocessor system in which, referred to as main 8086CPU processor, co-processor is referred to other processors. In this manner, does not directly provide 8086CPU a memory or I / O read and write control signals such as read and write commands, but the type of encoding of the current transfer operation to be performed is three bits is output from the bus controller 8288 decoding status signal to generate a corresponding control signal. Features mode of the system is the largest: bus control logic 8288 is generated by the bus controller and the control, i.e., the state of the main processor 8288 and a system bus signal into a command and control signals. Coprocessor only assist the main processor to complete some auxiliary work, that passively accept and execute commands from the host processor. 8086 coprocessor and supporting the use of two: one dedicated to numerical coprocessor 8087, and the other is dedicated to input and output operations of the coprocessor 8089.8087 high-precision floating-point integer arithmetic hardware. 8089 has its own set of dedicated input and output operations of the command system, also with a local memory, input and output devices may be directly service. Increase coprocessor, floating point and so that the input and output operations 8086 not take up time, thus greatly improving the efficiency of the system.
8086CPU pin definitions
1, AD15 ~ AD0 (addressdatabus): address / data bus, bi-directional, tri-state.
This is a set of time-sharing method for transmitting data multiplexed address or pins. The requirements of different clock cycles, determines the current is transferred to the memory cell access or I / O port address of the lower 16-bit, or 16-bit data transfer, or in a high impedance state.
2, A19 / S6 ~ A16 / S3 (address / status): address / status signal, the output tri-state.
This is a time-sharing method for transmitting multiplexed address or status pin. Wherein A19 ~ A16 of address bus 20 higher 4-bit address, S6 ~ S3 is a state signal. S6 denotes the CPU connected to a bus, S5 indicating the current state of the interrupt enable flag IF. S4, S3 code combination specified segment register is used currently in use. S4, S3 of code combinations and the corresponding segment registers case.
3, BHE (low) / S7 (bushighenable / status): allows high data transfer bus 8 / status signal, the output tri-state.
8-bit data bus high enable signal, when active low, indicates one byte of data transfer at a high 8-bit data bus D15 ~ D8. S7 is a signal state of the device.
4, RD / (read): read signal output, three state, active LOW.
Active low signal indicating that the operation in progress CPU memory read or read I / O ports.
5, READY (ready): ready signal input, active high.
READY signal is used to achieve matching the timing between the CPU and memory or I / O port. When the READY signal is active high, indicates that the CPU to access memory or I / O port is ready to work input / output data, CPU can read / write operations. When the READY signal is low, then the memory or I / O port is not ready, the CPU needs to insert a number of "TW state" wait.
6, INTR (interruptrequest): maskable interrupt request signal input, active high.
8086CPU each instruction executed when the last clock cycle, every detection signal INTR pin. INTR is high, indicating I / O devices to the CPU interrupt request, if IF = 1, CPU will respond to the interrupt, the current operation is stopped, an interrupt request of the I / O device service.
7, TEST / (test): waiting for the test control signal input, active LOW.
Signal used to support multi-processor system configuration, and for synchronizing between 8086CPU coprocessor functions, the CPU performs a WAIT instruction is used only if.
8, NMI (non-maskableinterrupt): non-maskable interrupt request signal is input, active high.
When there is a rising-edge trigger signal when the NMI pin, indicating that the internal CPU or I / O devices made of non-maskable interrupt request, the CPU will be executed after the current instruction, the immediate interrupt request.
9, RESET (reset): reset signal input, active high.
When the RESET signal is active, the CPU immediately ends the current operation in the reset state, initializes all the internal registers. States of the internal register after reset, when the RESET signal from high to low, the CPU restarts execution of the program starts from address FFFF0H.
10, CLK (clock): a clock signal input.
CLK provides basic timing pulse signal to the CPU. 8086CPU clock generator 8284A is generally used to generate a clock signal, a clock frequency of 5MHz ~ 8MHz, the duty ratio is 1: 3.
11, VCC power supply input pin.
8086CPU single + 5V supply.
12, GND: ground pin.
13, MN / MX / (minimum / maximum): Min / Max mode control input signal.
Pin to set the operating mode of 8086CPU. When a high level (access + 5V), CPU minimum working mode; when at a low level (ground), CPU operating at maximum mode.
- Minimum mode
Pin signal from the CPU used in the work mode is minimum, when the pin high, the minimum CPU operating modes. At this time, the meaning and function of the signal pins 24 to 31 are as follows:
1, M / IO / (memoryI / Oselect): memory, I / O port selection control signal.
Selection signal indicates the current CPU is accessing the memory access or I / O port. Is high, the memory access that represents the current data transfer to be performed between the CPU and the memory. It is low, access I / O ports, data indicating the current to be transferred between the CPU and I / O ports.
2, WR / (write): write signal, an output, active low.
Signal is active, indicating that the CPU is performing a write bus cycle, while the signal decision memory or I / O port performs a write operation.
3, INTA / (interruptacknowledge): maskable interrupt response signal output, active low.
A signal responsive to the CPU peripheral raised maskable interrupt request. Is low, it indicates that the CPU has responded peripheral interrupt request is about to execute the interrupt service routine.
4, ALE (addresslockenable): address latch enable signal, an output, active HIGH.
CPU ALE signal using the address information may lock AD15 ~ AD0 address / data, A19 / S6 ~ A16 / S3 address / status lines present in the address latch.
5, DT / (datatransmitorreceive): data transmission / reception signal, the output tri-state.
DT / signal is used to control the direction of data transmission. DT / is high, CPU transmits data to the memory or I / O port; DT / is low, CPU receives data from the memory or I / O port.
6, DEN / (dataenable): allowing the control data signal, an output, three state, active LOW.
The signal serves as the gate bus transceiver control signals. When low, it indicates that CPU data read / write operations.
7, HOLD (busholdrequest): a bus hold request signal input, active high.
In the DMA data transfer, the bus controller 8237A emitted from a high active bus request signal to the CPU HOLD input pin, so that the CPU requests control of the bus.
8, HLDA (holdacknowledge): bus hold signal in response to the output, active HIGH.
HOLD HLDA is used in conjunction with contact signal. In the effective period HLDA, HLDA output pin in response to an active high signal, while the bus is in a floating state, so that the control of the CPU bus, it will be delivered to the application controller 8237A using the bus, the bus use after, make HOLD signal goes low, CPU regained control of the bus.
- Maximum mode
When tied low, CPU operating in the maximum mode. At this time, the meaning and function of the signal pins 24 to 31 are as follows:
1, S2, S1, S0 (statussignals): bus cycle status signal, the output, active low.
2, RQ /, GT / (request / grant): bus request enable signal input / output bus request enable signal, two-way, active low.
This signal is used when the functions of the two signals HOLD substitution minimum pattern / HLDA, a multiprocessor system is specially designed. When a system component requires control of the bus right, the bus request signal is issued through the signal line to 8086CPU, if the CPU in response to a bus request, by sending back a response signal pin of the same, allowing the bus request, bus abandoned show 8086CPU the control, the control of the bus member to the proposed use of the bus request. RQ / GT0 priority than RQ / GT1.
3, LOCK / (lock) bus block signal output, active low.
Signal is active, represents a case 8086CPU other bus is not allowed to take the bus member.
4, QS1, QS0 (queuestatus): instruction queue status signal output.
Combination signal QS1 and QS0 may indicate the status of the bus interface unit BIU instruction queue, so that other processor monitors, track the status of the instruction queue.
8086 system components
8086 is a microprocessor, plus the necessary support chip, such as a clock generator, the address latch, the bus driver, memory and I / O interface, etc., in order to constitute a complete microcomputer. The complexity of the system and the number of the external device, the system 8086 can use two kinds of configuration mode, the maximum mode and the minimum mode. The minimum pattern is a single-CPU system, in such a system, all the control signals MN 8086 / MX pin high, the system directly by the CPU. The maximum pattern is a multi-CPU system, then MN / MX tied low, state information must be decoded by the CPU bus controller 8288 to produce the necessary system control signal.
1. Address Latch
8086 AD15 when AD0 address / data multiplexed lines, i.e., CPU and memory information exchange in the first state T1, first accesses the storage unit CPU sends address information AD15 to the AD0, followed by some lines to transmit data in so the data sent before the bus must first address latch up. 8282 or 8086 available 74LS373 latch unidirectional address AD15 ~~ AD0. 7-9 using three 8282 because the 8-bit latch 8282 having a function 8086 and having a 20-bit address and BHE signals. If the system memory capacity is small, less than 20 using the address information may be only two OE 8282. FIG grounded, so that the latch is always allowed output state. ALE output pin is connected to STB 8086. In the state of the bus cycle T1, the positive pulse on the ALE, the falling edge of its input address information 8282 stored in the latch, is fed by the output of the address bus.
2. bidirectional data bus driver
CPU can send data directly to a data bus. Without latch. In order to increase the bus load capacity, the CPU data bus generally plus drive and requires two-way drive, generally 8-bit bidirectional drive 8286 or 74LS245. Since the 8086 data bus is 16 bits, so use Ai pin connects two 8286.8286 of CPU of the ADi, which is the Di pins to the system data bus D1, and 8086 DT / R T pin connection 8286 when the DT / R to the high level, the data transmitted from the CPU to data bus .DT / R is low, CPU receives data of OE .8286 feet to 8086 feet from the DEN data bus. 8086 when DEN is low, input or output data allowed.
3. The clock generator / driver
8086 provides the desired frequency of the clock CLK output clock CLK from .8284 8284, depending on the frequency of X1, X2 crossover quartz crystal. In addition, 8284 also provides timing and width to meet the requirements of the RESET signal and the READY signal 8086 to meet the requirements.
4. The memory member
8086 1MB directly addressable memory space. This storage space is divided into two 512KB memory banks. A bank of units odd address, for storing data in the high byte 16, another by the even address memory bank units, for storing a 16-bit low byte of data. The former is called an odd memory address, which is called the even address memory bank. 8-bit data of the even address memory bank data bus connected to the CPU bus D7 D0, while the odd memory address 8-bit data to the data bus lines D15 D8. A19 ~~ A1 address lines simultaneously to the two banks, and even as A0 i.e., the address signal A0 = 0 is selected, the even bank is selected as an odd address .BHE chip select signal, BHE = 0, the odd bank is selected. Therefore, two banks can be read or written simultaneously, can select a single bank.
5.I / O end opening
A complete microcomputer system must have a device .I O I O device has a port address number / / .CPU port addresses sent through the address bus, the address decoder output through port, the port pins to the chip select and specify the selected .8086 port access to the memory according to the execution command is a command or command input and output, to make the M / IO control signal is high or low, in order to distinguish the address on the address bus is accessing memory or peripheral access.