Primer
What is interrupted
For life's little chestnut know that I am writing this document, the doorbell rang, I went down to open the door, turned out to be the courier, the courier after receipt of finished, then write back.
In the above example,
1. 我就是CPU
2. 编写文档，是主运行程序
3. 门铃响了，是中断信号
4. 查看到是快递，是查询中断号
5. 签收快递，是中断处理程序
6. 签收完快递后继续工作，是中断返回
That is, due to some events that interrupt the main CPU interrupt running programs run, and handle the event, the process continues to run after the main program.
Why break
The same with the above example, the interrupt remove that step 3 above step removed, that is, at the same time I need to write a document, take some time to go to the door to see if there is a courier, this process is very visible waste my time, efficiency is very low.
The purpose is to improve the interrupt CPU utilization. So you can understand why the interruption as short as possible.
What is interrupt priority
Also used the example above, if the doorbell rang colleagues, kitchen gas burning hot water also opened, then it needs a priority, such priority to turn off the gas.
Therefore, when multiple interrupts are triggered simultaneously, priority can tell which CPU the priority.
What is interrupt nesting
The example above, if I sign for delivery in the process, the open water, I go off the gas, continued to sign for delivery at the back, which is nested interrupts higher priority interrupt handling in the interrupt.
What is pushing and popping
Using the example above, when before I received courier, I go first book written document where the next record, and then to collect courier, to close finished, I work from a position of this re-yard record.
Wherein the book is a stack, the recording process is to stack the book, from the book is read out of the process stack.
Visible only one purpose, to restore the site to keep the harvested forget where express himself wrote.
Is a stack in memory management, after having advanced out backward site characteristics.
Cortex-M3 interrupt management
Cortex-M3 designed a very good interrupt system, the system abnormal (can be seen as a special interrupt) processing is very timely and convenient and disruption that NVIC (Nested Vectored Interrupt Controller).
In the relevant information of Cortex-M3, the exceptions and interrupts are separately described, here I put them merge instructions are interrupted as a point of view, because they feature too similar.
Vector interrupt support
- M3 interrupts are mapped to a variety of different addresses, when an interrupt occurs, M3 will look for the interrupt number from the table to address interrupt entry function, and then jump in the past and execution.
- On which address mapping is configurable, so when we modify the start address of the program, the interrupt vector must be remapped, such as boot + app development time.
- The following table, 1-15 for system exceptions, external interrupts for more than 16.
Can be nested interrupt support
Earlier learned that interrupt nesting and priority sealed inseparable.
A priority table above, the smaller the priority value M3, the higher the priority. Wherein the reset, and NMI priority hardware fault is fixed, and higher than other interrupts.
In theory, M3 supports three fixed +256 highest priority level programmable priority, while supporting 128 preemption. M3, after all, is due to embedded systems, chip manufacturers will be streamlined, smaller than the theoretical value at the time of implementation. So please forget the above figures, the actual situation of chip prevail.
Below, M3 in order to manage priorities,
1. 通过寄存器AIRCR为优先级分组，通过分组我们可以知道哪些bit代表抢占优先级，哪些bit代表亚优先级，如图中1->2->4。
2. 中断优先级寄存器阵列的每个寄存器都是8位的，映射到优先级分组后，如图中3->4，经过此映射，M3就知道每个中断的抢占优先级和亚优先级分别是多少了。
3. 当多个中断同时发生时，M3首先选择抢占优先级最高的中断执行，当抢占优先级相同的中断同时触发时，M3优先选亚优先级最高的执行。
4. 到此，我们也明白了为什么理论上优先级有256级，抢占优先级只有128个了。
Dynamic priority adjustment support
You can change the priority of an interruption in the program is running.
Maskable
Greatly reducing the interrupt latency
1. 向量化的设计，省去软件判断中断来源。
2. M3自动压栈和出栈R0-R3,R12,LR，PSR，PC寄存器，注意R4-R11需要手工入栈。
3. 优先级的有效合理分配，可以使需要的中断立马及时响应。
4. 咬尾中断和晚到中断机制，保证高优先级中断的实时响应。
5. 永不屏蔽的NMI（不可屏蔽中断），可以使系统第一时间做出响应，除非CPU挂了。
Interrupt
Comment:
If you understand the stack, the stack processes and priorities, then biting late arrival interrupts and interrupt mechanism like to understand.
Interrupt tail biting: Optimization of the stack, the stack is not directly run the higher priority interrupt, After completion of the higher priority process, once the stack together, and to cut out a process stack.
Late arrivals interrupt mechanism: optimization of the stack, the initial push higher priority interrupt is generated, the first push higher priority, high priority to improve the response speed.
Code configuration
Code below and above described correspondence, difficult to understand.
static VOID UART1_NvicConfiguration(VOID)
{
NVIC_InitPara NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQ = USART1_IRQn; /* 要配置的中断号 */
NVIC_InitStructure.NVIC_IRQPreemptPriority = 0; /* 抢占优先级 */
NVIC_InitStructure.NVIC_IRQSubPriority = 0; /* 亚优先级 */
NVIC_InitStructure.NVIC_IRQEnable = ENABLE; /* 使能控制 */
NVIC_Init(&NVIC_InitStructure);
}