Dynamic power optimization

https://mp.weixin.qq.com/s?__biz=MzUzODczODg2NQ==&mid=2247484666&idx=1&sn=1f3a7301f556468bc1cb0f222a8965e6&chksm=fad26d24cda5e432b8cc785ab56ddfbc73a106cc3f680b5632219244ca1e8b6555bfa7caa7cc&scene=21#wechat_redirect

https://mp.weixin.qq.com/s/t93z1cIuQIxDLUhsn4eCKg

In terms of chip, power consumption is not only energy problem, it will seriously affect the reliability, performance and cost. And directly related to handheld devices, power consumption must be taken seriously is one performance indicator, standby time. Therefore, power consumption in the chip architecture of the birth process from algorithm design to achieve the packaging and testing from start to finish is eagerly cared for. Cliché: 80% of the power consumption of the chip control algorithm depends on the architecture part of the "soul" and "labor" only 20% of space to play.

 Digression: up only 10% of silicon farmers can master the "soul", and that the remaining 90% is labor, day and night they bored while carrying a brick, almost no middle path, everything depends on the initial decision. That 10% is Gaoshanyangzhi, donkeys can not match, we can only do plain discussion about the labor thing.

 

 

While laborers not touch the soul, but no lack of spirit of exploration, they do everything in their talent and 20% of the space, to explore a set of methods to optimize power consumption. The following table lists the current mainstream method to optimize power consumption and design, implementation, verification affect all aspects. Deals with dynamic power optimization, or need to start from the composition and calculation formula corresponding dynamic power consumption, when a certain operating voltage and frequency that optimizes dynamic power consumption primary goal is to try to reduce the toggle rate, in addition to internal power also need to minimize the load input with the output pin of the transition, of course, is to minimize power consumption of the load the load capacitance. Based on this embodiment there are several substantially optimized dynamic power:

  • clock gating: by far still the most effective way.

  • multi bit merge: the need to support the library.

  • activity driven power optimize: need to read activty file

  • Multiple voltage domain (MSV): need power intent support.

  • Dynamic voltage frequency scaling (DVFS): need power intent support.

 

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Origin www.cnblogs.com/lelin/p/11410141.html