In xilinx template, there is a sample Aurora engineering, comprising a number of sub-functions, one by one in this series will herein be parsed, aurora_8b10b_0_FRAME_GEN first function, according to the official description, its role is: This is a pattern generator module, with laser designed to test the hardware. It is generated by a laser and data channels. If the interface is connected to the frame, it generates frames of different sizes and spacing. LFSR for generating pseudo-random data, LFSR REM is connected to the lower bus.
REM should be here in the meaning of Remaining, LL_IP_REM output interfaces to the next module, so as to their value TKKP 10 or 11, it is through postpartum data is more random.
1, the management module reset
//*********************************Main Body of Code********************************** always @ (posedge USER_CLK) begin if(RESET) channel_up_cnt <= `DLY 5'd0; else if(CHANNEL_UP) if(&channel_up_cnt) channel_up_cnt <= `DLY channel_up_cnt; else channel_up_cnt <= `DLY channel_up_cnt + 1'b1; else channel_up_cnt <= `DLY 5'd0; end assign dly_data_xfer = (&channel_up_cnt); //Generate RESET signal when Aurora channel is not ready assign reset_c = RESET || !dly_data_xfer;
RESET reset input signal for the module, in addition, aurora ip channel_up also produces a signal output, the signal for official meaning:. Asserted when Aurora 8B / 10B channel initialization is complete and the channel is ready for data transfer tx_channel_up and rx_channel_up are only applicable to their respective simplex cores., is set when a CHANNEL_UP Aurora 8B / 10B channel initialized and ready for data channel transmission.
When 16 clock delay waiting for channel_up, & channel_up_cnt represents the respective phase, i.e., each bit 1, where it is delayed so that the frame data generating unit reset operation.
2, the random data generation module
Is a LFSR (linear feedback shift register, LFSR) generates a random number have concerns
//______________________________ Transmit Data __________________________________ //Generate random data using XNOR feedback LFSR always @(posedge USER_CLK) if(reset_c) begin data_lfsr_r <= `DLY 16'hABCD; //random seed value end else if(!TX_DST_RDY_N && !idle_r) begin data_lfsr_r <= `DLY {!{data_lfsr_r[3]^data_lfsr_r[12]^data_lfsr_r[14]^data_lfsr_r[15]}, data_lfsr_r[0:14]}; end
The simulation (modelsim) results
3, the frame data of the transmission data number counter counter
Using the official architecture always two blocks, a maximum number of data always block of each frame of data transmitted, and the other always block count of the number of data has been transmitted, when data is representative of a value of the counter is equal to two Sent.
Code:
//Use a counter to determine the size of the next frame to send always @(posedge USER_CLK) if(reset_c) frame_size_r <= `DLY 8'h00; else if(single_cycle_frame_r || eof_r) frame_size_r <= `DLY frame_size_r + 1; //Use a second counter to determine how many bytes of the frame have already been sent always @(posedge USER_CLK) if(reset_c) bytes_sent_r <= `DLY 8'h00; else if(sof_r) bytes_sent_r <= `DLY 8'h01; else if(!TX_DST_RDY_N && !idle_r) bytes_sent_r <= `DLY bytes_sent_r + 1;
Further, in the data transmission process using a counter to generate a ifg_size_r, 15 such that each ifg_size_c clock produces a high level of a clock, the refresh control signal controls the frequency of the signal values. (Personal understanding)
//Use a freerunning counter to determine the IFG always @(posedge USER_CLK) if(reset_c) ifg_size_r <= `DLY 4'h0; else ifg_size_r <= `DLY ifg_size_r + 1; //IFG is done when ifg_size register is 0 assign ifg_done_c = (ifg_size_r == 4'h0);
4, hot code state machine
This always block the transfer of the control state, the state of the output signal of this control signal transmitted (mainly generated and Tlast Tvalid signal)
//State registers for 1-hot state machine always @(posedge USER_CLK) if(reset_c) begin idle_r <= `DLY 1'b1; single_cycle_frame_r <= `DLY 1'b0; sof_r <= `DLY 1'b0; data_cycle_r <= `DLY 1'b0; eof_r <= `DLY 1'b0; end else if(!TX_DST_RDY_N) begin idle_r <= `DLY next_idle_c; single_cycle_frame_r <= `DLY next_single_cycle_frame_c; sof_r <= `DLY next_sof_c; data_cycle_r <= `DLY next_data_cycle_c; eof_r <= `DLY next_eof_c; end
idle_r = 0 indicates an idle state, no data transmission, idle = 0 represents a frame of data, single_cycle_frame_r indicates a new data transmission is ready to start, sof_r indicating the start of a frame of data starts, data_cycyle_r indicates data transfer in progress, eof_r represents data transfer is completed.
//Nextstate logic for 1-hot state machine assign next_idle_c = !ifg_done_c && (single_cycle_frame_r || eof_r || idle_r); assign next_single_cycle_frame_c = (ifg_done_c && (frame_size_r == 0)) && (idle_r || single_cycle_frame_r || eof_r); assign next_sof_c = (ifg_done_c && (frame_size_r != 0)) && (idle_r || single_cycle_frame_r || eof_r); assign next_data_cycle_c = (frame_size_r != bytes_sent_r) && (sof_r || data_cycle_r); assign next_eof_c = (frame_size_r == bytes_sent_r) && (sof_r || data_cycle_r);
Dure code form using the state machine switches to generate signals in accordance with which the last valid state and