Known 8 NC divider. When the width of the positive and negative output pulse square wave input data are controlled by two 8:
Top of the application:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity wide is
port(
clk1:in std_logic;
d1:in std_logic_vector(7 downto 0);
d2:in std_logic_vector(7 downto 0);
four1:out std_logic
);
end;
architecture one of wide is
component dvf
port(
clk:in std_logic;
d:in std_logic_vector(7 downto 0);
four:out std_logic
);
end component;
component or2a
port(
A,B:in std_logic;
c:out std_logic
);
end component;
signal full1,full2:std_logic;
begin
u1:dvf port map(clk=>clk1,d=>d1,four=>full1);
u2:dvf port map(clk=>clk1,d=>d2,four=>full2);
u3:or2a port map(A=>full1,B=>full2,C=>four1);
end;
The underlying program:
Or door:
library ieee;
use ieee.std_logic_1164.all;
entity or2a is
port(
A,B:in std_logic;
C:out std_logic
);
end entity or2a;
architecture one of or2a is
begin
c<=a or b;
end architecture one;
8 NC divider;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dvf is
port(
clk:in std_logic;
d:in std_logic_vector(7 downto 0);
four:out std_logic
);
end;
architecture one of dvf is
signal full:std_logic;
begin
p_reg:process(clk)
variable cnt8:std_logic_vector(7 downto 0);
begin
if clk'event and clk='1' then
if cnt8="11111111" then
cnt8:=d;
full<='1';
else cnt8:=cnt8+1;
full<='0';
end if;
end if;
end process p_reg;
p_div:process(full)
variable cnt2:std_logic;
begin
if full'event and full='1' then
cnt2:=not cnt2;
if cnt2='1'then four<='1';
else four<='0';
end if;
end if;
end process p_div;
end;
Its original RTL:
The simulation diagram:
