Classic Timing Analysis Model
1. setup time edge and hold time edge
reg a source register
reg b destination register, there is a common clock source
2.4 kinds of timing path
PPT1
The fourth combination is a pure path
The first three categories are of the same class
PPT2
3. Data Arrival Time
PPT1
H Tdata is a wiring delay and logic delay and delay logic
PPT2
Captured along
Settling Time Requirements
4. hold time requirements
Th is present at least after the data arrives, the new data can not be too early to
The margin is calculated
PPT1
A margin of time
The new data can not arrive too early, or else destroyed
PPT2
Margin calculation
The holding time is the time of arrival of the data arrival time in a
6. Analysis Slack negative situation
- Delay too much, setup slack data is negative circumstances
- Clock delayed too much, hold slack is negative circumstances
7. The two concerns delay
Tlogic and our code style, design-related, Tnet and layout related
Three system clock frequency and the amount of related
8. Conclusion
