Virtex5 FPGA package name and IO
Author: AirCity 2020.2.1
[email protected] owned by all the authors, Aircity
PINCH=1mm；
600 XC5VLX330 differential pair IO or IO 1200
Pin naming convention:
# IO_LxxY_
the IO: the IO the PIN
LxxY: XX differential pair number, Y = P or N, the polarity
#: represents Bank
# IO_LxxY_ZZZ_
the IO: the IO the PIN
LxxY: XX differential pair number, Y = P or N, polarity identification
ZZZ: pins corresponding to different functions, such as Dn, AddRn, FCS_B; for Clock Cable IO, ZZZ = CC, for Global Clock buffers, ZZZ = GC
#: represents the Bank
VRP a resistor R connected to VCCO, the value of R is equal to or twice the trace impedance trace impedance
VRN a resistor R connected to GND, the value of R is equal to or twice the trace impedance trace impedance.
GC: global clock pins, belongs to the global clock resources. GC into the FPGA, there BUFG buffers, each buffer clock specially limited resources, to minimize the time difference skew, jitter Jitter minimum, FPGA's reach.
CC: local clock, the clock can only provide input for the bank is located and adjacent to the bank. clock into the CC, after around BUFG clock the other bank.
