1 X86 and X87 Encyclopedia assembly instructions (annotated)
2 ---------- a data transfer instruction ----------------------- -----------------------------
3 which transfer data between memory and registers, registers and input and output ports.
41 universal data transfer instruction.
. 5 MOV word or byte transferred.
. 6 MOVSX first sign extension, and then transmitted.
. 7 MOVZX to doing it first zero-extended, and then transmitted.
. 8 words to the PUSH onto the stack.
. 9 word pops the stack to the pOP.
10 to PUSHA AX, CX, DX, BX, SP, BP, SI, DI are sequentially pushed onto the stack.
. 11 POPA the DI, SI, BP, SP, BX, DX, CX, AX are sequentially popped from the stack.
12 is PUSHAD the EAX, ECX, EDX , EBX, ESP, EBP, ESI , EDI sequentially pushed onto the stack.
13 is POPAD the EDI, ESI, EBP, ESP, EBX, EDX, ECX, EAX sequentially popped from the stack.
order 14 BSWAP exchange 32 byte register
15 XCHG exchange word or byte. (at least one operand register, a segment register as an operand is not available)
16 to exchange and compare the CMPXCHG operation (second operand must accumulator AL / AX / EAX)
17 XADD first exchange and then accumulated. (Result operand in the first)
18 is the XLAT byte look-up table conversion .---- BX pointing to the starting point of a 256 byte table, AL table index value (0- 255, i.e., 0-FFH); return result AL is a lookup table ([BX + AL] -> AL).
. 19 2. transfer instruction input and output ports.
20 is the IN the I / O port input (syntax:. IN accumulator { } port number │DX)
21 is OUT the I / O port output (syntax: OUT {port number │DX}, when the accumulator) input and output ports specified by the immediate embodiment, the scope thereof is 0-255; specified by the register DX,. . 0-65535 range
23 3. destination address of the transfer instruction.
23 is charged with the LEA effective address Example: LEA DX, string; the offset address stored to the DX..
24 transmits the LDS destination pointer, the pointer is loaded into the DS. Example: LDS SI, string; the address segment: offset address to keep the DS: the SI
25 the LES transmits the destination pointer, the pointer is loaded into ES Example: LES DI, string; the address segment: offset address to the stored ES .: the DI
26 is the LFS transfer destination pointer, the pointer is loaded into the FS Example: LFS DI, string; the address segment: offset address to the stored FS: the DI.
27 the LGS transfer destination pointer, the pointer is loaded in the GS embodiment. : LGS DI, string; the address segment: offset Access to the deposit GS: DI.
28 LSS transmission destination pointer, the pointer is loaded into the SS Example: LSS DI, string; the address segment: offset address to the stored SS: the DI.
47 the ASCII code to adjust the AAS subtraction.
29 4. flag transfer instruction.
30 LAHF flag Transfer register, the flag is loaded AH.
31 SAHF flag register transfer, the flag is loaded into register AH.
32 PUSHF mark stack.
33 is a stack of POPF flag.
34 is the PUSHD flag stack 32.
35 32 flag the POPD the stack.
36 ------- --- Second, arithmetic instructions ------------------------------------------ ----------
37 [the aDD adder.
38 is the ADC Carry.
39 plus INC. 1.
the ASCII code of the adder 40 AAA adjustment.
41 is the addition of the DAA decimal adjustment.
42 is the SUB subtraction.
43 is Steel Business Briefing with borrow subtraction.
44 is DEC Save 1.
45 NEG negated (0 minus it).
comparison 46 CMP. (two operand subtract, modify only flag is not sent back results).
49 the MUL unsigned multiplication result loopback AH and AL (byte operation), or DX and AX (word operation),
. Decimal adjust 48 DAS subtraction
50 IMUL integer multiplication result loopback AH and AL (byte operation), or DX and AX (word operations),.
The ASCII code adjustment 51 AAM multiplication.
52 is the DIV unsigned division result loopback: Suppliers loopback AL, remainder loopback AH, (byte operation); or commercially loopback AX, the remainder loopback DX, (word operations).
53 is the IDIV integer division results loopback: List loopback AL, remainder loopback AH, (byte operation); or. List loopback AX, the remainder loopback DX, (word operations).
the ASCII code adjustment 54 AAD division.
55 CBW bytes into words. (extended AL bytes symbols into AH go)
56 is CWD words into a double word . (extended symbols AX of the words in the DX go)
57 is CWDE words into a double word. (extended character number in AX in EAX to)
58 the CDQ double word expansion. (the value in EAX word symbol to go extended EDX)
59 ---------- three, logical operation instructions ---------------------------- ------------------------
60 and the aND operator.
61 is oR oR operation.
62 is the XOR exclusive oR operation.
63 is the NOT negated.
64 the tEST testing (two operands aND operation, only the modified flag, does not echo the result).
65 SHL logical shift left.
66 SAL Arithmetic Shift Left. (= SHL)
67 logical shift right the SHR.
68 SAR arithmetic shift right. (= The SHR)
69 the ROL Rotate Left.
70 ROR Rotate Right.
71 is RCL rotated left through the carry bit.
72 by the RCR carry Rotate right.
73 above eight kinds of shift instructions, the number of up to 255 times its displacement.
74 shift once opcode can be directly used as SHL AX, 1.
75 shift> 1, then It is given by the number of shift register CL.
76 as CL MOV, SHL AX 04, CL
77 ---------- four string instruction ---------------- ------------------------------------------
78 the DS: the SI source string segment register : index source string
79 ES: DI target string segment registers: target string index.
80 repetitions counter the CX.
81 AL / AX scan value.
82 D flag 0 indicates operation is repeated SI and DI should automatically increment; 1 represents should automatically decrement.
83 Z flag for controlling the scanning or compare operation ends.
84 MOVS string transfer. (MOVSB transmitted characters. MOVSW transmitted word. MOVSD transfer double words.)
85 CMPS Compare strings. (CMPSB comparing character. CMPSW comparand.)
86 the SCAS scan string with the contents of the AL and the AX or target string for comparison, which is reflected in the flag bit.
87 charged with the LODS string. the elements in the source string (word or byte) individually charged or AX, AL. (LODSB transmitting characters. LODSW transmitted word. LODSD transfer double words.)
88 STOS stored string. a LODS inverse process.
89 REP when CX / ECX <> 0 is repeated.
90 the REPE / REPZ when ZF = equal 1 or comparison result, and CX / ECX <> repeat 0:00.
91 is REPNE / REPNZ when ZF = 0 or the comparison result is not equal, and the CX / ECX <> 0 is repeated.
92 REPC when CF = 1 and CX / ECX <> 0 is repeated.
93 <> repeat REPNC when CF = 0 and CX / ECX 0 when.
97 cALL procedure call
98 RET / RETF process returns.
94 ---------- five program branch instruction ---------------------------------------------- ------
95 1. unconditional jump instruction (transfer length)
96 the JMP an unconditional branch instruction
transfer 114 JNO time does not overflow.
99 2. A conditional branch instruction (short transfer distance of -128 to +127) (iff (SF XOR OF) = time 1, OP1 <OP2)
when 100 JA / JNBE is not less than or equal to transfer.
101 JAE / JNB greater than or equal to transfer.
102 JB / JNAE less than metastasis.
103 the JBE / JNA less than or equal to transfer.
104 above four test unsigned integer arithmetic result (flag C and the Z).
105 JG / JNLE greater than metastasis.
106 JGE / JNL greater than or equal to transfer.
107 JL / JNGE less than metastasis.
108 the JLE / JNG less than or equal to transfer.
109 above four test signed integer arithmetic result (sign S, O and the Z).
110 JE / JZ equal transfer .
transfer when 111 JNE / JNZ not equal.
transferred during 112 JC there is a carry.
113 JNC transfer when no carry.
transfer odd 115 JNP / JPO parity is.
transferred during 116 JNS sign bit is "0."
117 JO overflow transfer .
118 JP / JPE transfer parity is even.
119 transfers the JS sign bit is "1".
120 3. The control instruction cycle (short transfer)
121 LOOP cycle when the CX is not zero.
122 LOOPE / LOOPZ the CX is not zero, and flag Z = cycles. 1.
123 LOOPNE / LOOPNZ the CX is not zero flag Z = 0 and the loop.
transfer 124 JCXZ CX when zero
transition time 125 jECXZ ECX zero.
126 4. interrupt instruction
127 INT interrupt instruction
128 INTO overflow interrupt
129 IRET interrupt return
130 the processor control instructions
131 HLT processor is halted until a reset signal or an interrupt before continuing.
132 when the wAIT TEST chip leads to a high level so that the CPU into a wait state.
133 to the outside of the ESC conversion process device.
134 blocked the LOCK bus.
137 the CLC clear the carry flag.
135 the NOP No operation.
136 STC the carry flag.
138 inverse of the CMC carry flag.
139 STD direction flag is set.
140 CLD clear direction flag.
141 is the STI interrupt enable bit is set.
142 the CLI Interrupt Enable bit cleared.
143 ------- --- six directive ------------------------------------------- ---------------
144 DW defining word (2 bytes).
145 define the PROC process.
end 146 ENDP procedure.
147 sEGMENT definition segment.
148 to establish the ASSUME segment register addressing.
149 eNDS period ends.
150 the eND routine ends.
151 ---------- seven, the processor control instructions: processing instruction flag --------------------- ---------------
152 into bit position 0 command the CLC
153 CMC negated carry bit instruction
154 STC command into bit position 1
155 CLD direction flag set instruction
170 WAIT synchronous CPU and FPU machine code 9B
156 STD direction command flag 1
0 157 CLI command interrupt flag
158 STI instruction interrupt flag
159 NOP No operation
160 HLT stop
161 WAIT Wait
162 ESC Escape
163 LOCK block
164 floating point instruction set ========== === ================================================== =
165 ---------- a control command (control command with the prefix 9B FN floating point F becomes not checked, machine code remove 9B) ----
166 FPU machine code to initialize the FINIT DB E3. 9B
167 FCLEX clear exception DB E2 machine code. 9B
168 FDISI floating-point inspection machine code disables interrupts DB E1. 9B
169 FENI floating-point inspection disable interrupts two DB E0 machine code. 9B
171 FWAIT synchronous CPU and FPU machine code D9 D0
172 FNOP no operation E9 Encoding the DA
173 exchange FXCH ST (0) and ST (1) Encoding C9 D9
174 FXCH ST (i) exchange ST (0) and ST (i) Encoding C1iii D9
175 FSTSW ax ax state machine code word to the DF E0 9B
176 mem FSTSW word PTR state machine code word to mem DD mm111mmm 9B
177 FLDCW word word PTR state machine code to mem mem mm101mmm D9
178 FSTCW control word word PTR mem mem machine code to D9 mm111mmm 9B
179
180 [FLDENV Word PTR mem mem machine code to a full environmental D9 mm100mmm
181 FSTENV word ptr mem mem whole environment to machine code D9 mm110mmm 9B
192 FLDPI π charged to ST (0) machine code D9 EB
182 FRSTOR word ptr mem mem FPU state machine code to DD mm100mmm
183 FSAVE word ptr mem FPU state machine code to mem DD mm110mmm 9B
184
185 FFREE ST (i) flag ST (i) Encoding unused C0iii DD
186 FDECSTP reduce stack pointer 1-> 02-> 1 Encoding F6 D9
187 increasing the stack pointer FINCSTP 0-> 1 1-> 2 Encoding F7 D9
188 FSETPM floating point E4 protective machine code DB
189 ---------- Second, the data transfer instruction -------- --------------------------------------------
190 FLDZ charged to 0.0 ST (0) Encoding EE D9
191 FLD1 charged 1.0 ST (0) Encoding E8 D9
193 FLDL2T the ln10 / ln2 charged ST (0) Encoding E9 D9
194 FLDL2E the 1 / ln2 charged ST (0) machine code D9 EA
195 FLDLG2 the ln2 / ln10 charged ST (0) EC machine code D9
196 FLDLN2 ln2 charged to ST (0) machine code ED D9
197
198 FLD REAL4 PTR mem mem load of single-precision floating Encoding mm000mmm D9
199 FLD real8 ptr mem mem is loaded into machine code, double precision floating point mm000mmm DD
200 is loaded FLD REAL10 PTR mem mem ten byte floating point mm101mmm machine code DB
201
202 FILD Word PTR mem mem loaded machine code two-byte integer DF mm000mmm
203 FILD DWORD PTR mem mem charged four-byte integer mm000mmm machine code DB
204 FILD eight-byte integers Encoding DF qword ptr mem mem is loaded mm101mmm
205
206 FBLD Tbyte PTR mem mem ten bytes loaded machine BCD mm100mmm code DF
207
208 FST real4 ptr mem mem save single float machine code to mm010mmm D9
209 to save the FST REAL8 PTR mem mem machine code into double precision floating point mm010mmm DD
210
211 save the FIST Word PTR mem mem machine code to two-byte integer mm010mmm the DF
212 FIST dword ptr mem mem to save four byte integer mm010mmm machine code DB
213
214 FSTP REAL4 PTR mem mem saved to single precision floating point stack and the machine code mm011mmm D9
215 FSTP REAL8 PTR mem double precision floating point saved to the stack and mem Encoding mm011mmm DD
216 FSTP REAL10 PTR mem mem to save ten byte floating point stack and the machine code mm111mmm DB
217
220 stored mem PTR QWORD the FISTP eight-byte integers and a stack machine code to mem mm111mmm DF
221
218 the FISTP Word PTR save two mem mem-byte integer to the stack and the machine code DF mm011mmm
219 FISTP dword ptr mem four-byte integers stored to the stack and mem mm011mmm machine code DB
231 FCMOVU ST (0), when the transfer machine code DA D1iii ST (i) random
222 FBSTP tbyte ptr mem save ten BCD bytes to the stack and machine code mem mm110mmm the DF
223
224 FCMOVB transfer machine code DA C0iii ST (0), ST (i) < When
225 FCMOVBE ST (0), ST (i) <= machine code when transmitting D0iii the DA
226 FCMOVE ST (0), ST (I) when the transfer machine code DA C1iii =
227 FCMOVNB ST (0), ST (i)> = machine code when transmitting C0iii DB
228 FCMOVNBE ST (0 ), ST (i)> when the machine code transmitted D0iii DB
229 FCMOVNE ST (0), ST (i)! = C1iii transfer when the machine code DB
230 FCMOVNU ST (0), DB machine code when ordered transfer ST (i) D1iii
232 ---------- Third, the comparison instruction ----------------------------------- ---------------------
233 the FCOM ST (0) -ST (. 1) Encoding Dl D8
234 the FCOMI ST (0), ST (I) ST (0 ) -ST (1) F0iii machine code DB
235 FCOMIP ST (0), ST (I) ST (0) -ST (1) and the stack machine code F0iii the DF
236 REAL4 the FCOM PTR mem ST (0) - real machine mem mm010mmm code D8
237 REAL8 the FCOM PTR mem ST (0) - real machine code mem mm010mmm the DC
238
239 FICOM Word PTR ST mem (0) - mem integer Encoding mm010mmm DE
240 FICOM DWORD PTR mem ST (0) - mem integer Encoding mm010mmm the DA
241 FICOMP Word PTR ST mem (0) - mem integer and the stack machine code DE mm011mmm
242 FICOMP DWORD PTR mem ST (0) - mem integer and the stack machine code DA mm011mmm
243
244 FTST ST (0) -0 Encoding D9 E4
245 FUCOM ST (i) ST ( 0) -ST (i) machine code E0iii DD
246 FUCOMP ST (I) ST (0) -ST (I) and the stack machine code E1iii DD
247 FUCOMPP ST (0) -ST ( 1) and a second stack machine code E9 the DA
248 FXAM ST (0) Specifications type E5 Encoding D9
249 ---------- four arithmetic instructions ------------ --------------------------------------------
250 the destination operand of FADD (attached directly to the command variable or stack register) and the source operand (connected to the destination operand stack variables or buffer) are added, and the result in the destination operand
251 FADDP ST (i), ST this directive is the destination operand plus ST buffer, and pop ST buffer, while the destination operand must be one in which the stack buffer, regardless of the final destination operand why, after the pop-up once, will become the destination operand a buffer on the stack to
256 FSUBR minuend and subtrahend interchanged
257 FSUBRP
252 FIADD FIADD is the source operands plus ST, ST and then stored in the buffer, the source operand must It is an integer, or short integer block form variable
253
254 FSUB Save
255 FSUBP
258 FISUB
259 FISUBR
260.
261 by FMUL
262 FMULP
263 FIMUL
264
265 except FDIV
266 FDIVP
267 FDIVR
268 FDIVRP
269 FIDIV
270 FIDIVR
271
272 FCHS positive and negative changes of ST
273
274 ST the value of the FABS removed the absolute value is then stored back.
275
276 ST value of the FSQRT removed, and then stored back square root.
277
This command is calculated 278 FSCALE ST * 2 ^ ST (1) of the value, and then stores the result in ST and ST (1) of the same value. ST (1) must be an integer between -32768 and 32768 (-215 to 215), if the calculation result exceeds this range can not be determined, if not an integer ST (1) will first rounded into integers zero recalculated. Therefore, for safety reasons, preferably an integer of loading a word into ST (1) inside.
279
280 FRNDINT This command is a value of the ST is rounded into integers, FPU provides four rounding mode, determined by the FPU control word (control word) two bits of RC
281 is round control RC
28200 rounding
28301 to negative infinity rounding
28410 rounding to positive infinity
28,511 to zero rounding
286 ================
a sub open subroutine procedure
sub esp, 0x40 leaving room in the stack of local variables.
The word ebx the PUSH onto the stack register ebx
push ebp ebp register contents into
move ebp, dword ptr ds: [ ] transmission word or byte to register ebp