1. process flow:
The input data stream "the input data selection unit" and the like assigned to the two data streams by the data buffer , the data buffer memory module may be any module, commonly used memory cell is the dual-port RAM (DPRAM), single-port RAM (SPRAM) , FIFO and so on. In the first cycle the buffer, the input data to the stream buffer "the data buffer module 1"; in the second buffer cycle, by switching the "input data selection unit", the data input to the stream buffer "Data Buffer Module 2 ", while the" data buffer module 1 "in the first cycle cache data", "selected to" output data selecting unit streams arithmetic processing module "arithmetic processing; in the third buffer cycle through the" input data selecting means "of the switch again, the data input to the stream buffer" the data buffer module 1 ", while the" data buffer module 2 "in the second data buffer cycles through" the output data selecting means "switch to" data stream arithmetic processing module "for arithmetic processing. So the cycle.
2. Features:
By "the input data selection unit" and "output data selecting means" according to the beat, cooperating switch the buffered data stream without stopping to the "data stream arithmetic processing module" in operation and processing. The ping-pong operation module as a whole, standing at both ends of the module to see the data, the input data stream and output data stream is continuous, without any pause, so it is suitable for processing pipelined data stream. Therefore ping-pong operation is often applied to a pipeline algorithm, complete seamless data buffer and processing.
3. Advantages:
You can save buffer space. For example, in WCDMA baseband applications, a frame is composed of 15 slots, the data may need to be a full frame of a time slot delay after the processing, more direct approach is to put the frame data buffer together, then the delay 1 slot is processed. In this case the length of the buffer is a full frame of data length, assume that the data rate is 3.84 Mbps, a frame length of 10ms, the required buffer length at this time is 38,400. If a ping-pong operation, only two can be defined. 1 slot buffer RAM data (can be one-port RAM). When writing data to a RAM, a RAM read data from another, and then to the processing unit, when the capacity of each RAM 2560 can only, add up to only two RAM 5120 capacity.
Substantial low speed high speed data processing module by the ping-pong operation is: to achieve a string of data flow through the DPRAM buffer unit, and this conversion is the embodiment of the principles of the area of the exchange rate!
