I. Review
On the one we are talking about the PCIE protocol analysis points to some preliminary knowledge, the following content is difficult to understand, these contents to the latter when it comes to the actual code that I will give you elaborate, and here if you really can not understand it Not force.
- PCI-E configuration space
- PCI-E address map
- PCI-E BAR BAR register and space
- PCI-E elaborate hierarchy
Two, PIO XAPP1052 XDMA three links and differences dwell
Because we're going to analyze the TLP packet format, and the latter to learn PIO XAPP1052 XDMA three engineering source code, and now some people even do not know what these three, so that the next course PIO XAPP1052 XDMA three ties and differences in advance.
(1) PIO
PIO English spelling "Programming Input / Output Model", PIO mode is a write mode for data exchange by the CPU performing the data I / O port instruction. PIO example, our host PC, FPGA from the machine , the functions that read and write PFGA PC register or RAM. Like STM32 serial register the same operation, STM32 for the host serial port from the machine, so to achieve functionality tightly. PIO example contains a PCIE IP Core, our user interface through AXI Stream Interface (late fourth quarter will explain in detail) can interact and PCIE IP Core and send and receive data. As for how the analysis code logic to achieve.
（2）XAPP1052
XAPP1052 applications is a DMA of the PCIE xilinx provide, in addition to the PIO function, but also added a DMA controller, the DMA controller can direct data exchange such as FPGA, and the host PC memory (of course, which requires the host bridge HOST help, we'll be called the strongest aid , which implements a lot of features, but we do not know). After that we can read and write PC DMA controller inside the FPGA PIO mode, DMA controller receives a DMA operation transmitted from PC address, length of operation, the operation command, began as a main PCIE