Q：
DU teachers Hello, on MATLAB and FPGA implementation of digital filters (Altera edition) book some questions to ask:
In section 7.4.3 of the adaptive equalizer verilog implementation, there is a process of student really can not be understood, that when the filter output signal and the error signal is obtained:
begin
Y1_out <= {{3 {Y_Reg [0] [31]}}, Y_Reg [0]} + {{3 {Y_Reg [1] [31]}}, Y_Reg [1]} + {{3 {Y_Reg [2 ] [31]}}, Y_Reg [2]};
Y2_out <= {{3 {Y_Reg [3] [31]}}, Y_Reg [3]} + {{3 {Y_Reg [4] [31]}}, Y_Reg [4]} + {{3 {Y_Reg [5 ] [31]}}, Y_Reg [5]} + {{3 {Y_Reg [6] [31]}}, Y_Reg [6]};
Y_out <= Y1_out + Y2_out;
if (count==3)
E_out <={{5{Rin_Reg[3][15]}},Rin_Reg[3]}-Y1_out[34:14]-Y2_out[34:14];
end
Wherein, for example, {{3 {Y_Reg [0] [31]}}, Y_Reg [0]} is the mean of the results of the 0 passage Y_Reg sign bit replicated three times and then placed in their upper right splicing? Now students do not understand why is copied three times to put such a high operating?
There calculated DW _REG when [n-] DW_Reg [n-] <= - {{{7 Xin_Reg [n-] [15]}}, Xin_Reg [n-] [15: 7]}; in the most significant bit is copied seven discharge at a high level.
The teacher can also ask for taking over to help students appreciate it!
A：
This is just a sign extension operation VERILOG. Since the operand is signed data, thus expanding the sign bit does not change the size of the positive and negative values, while expanding to the desired bit width.
Congratulation funny!
DU Yong
