I2C is a serial data communication protocol developed by Philips invention, using only two signal lines: SerialClock (referred to as SCL) and the serialData (referred to as SDA). I2C is a bus structure, a Master, Slave 1 or more, each Slave device to distinguish the 7-bit address, a write back address talk bit indicates a read (= 1) or write (= 0), we sometimes you can see eight forms of device address, then each device to read, write both addresses, high 7-bit address is actually the same.
I2C data format is as follows:
No data: SCL = 1, SDA = 1 ;
start bit (the Start): When SCL = 1, SDA transitions from the 1 to 0;
stop bit (the Stop): When SCL = 1, SDA by the 0 to 1 transition;
data bits: when the SCL transition from 0 to 1, controlled by the sender SDA, SDA is valid data at this time, not free to change SDA;
while SCL remains is 0, the data on the SDA can be freely change;
address: it defines with data bits, but only issued by the Master Slave;
acknowledge bit (the ACK): when the sender transmits End 8 bits, the sender releases SDA, SDA controlled by the receiver, and SDA = 0;
no acknowledge bit (NACK): when the sender transmits Ends 8, the sender releases SDA, SDA controlled by the receiver, and SDA = 1.
When the data transfer is a single byte format:
start bit, 8 address bits (including a write bits), the response, 8-bit data, response, stop bits.
When the data transmission is a string of bytes, the format:
start bit, 8 address bits (including a write bits), the response, 8-bit data, response, 8-bit data, response, ......, 8-bit data, answer, stop bits.
have to be aware of is:
1, SCL has been controlled by the Master, the direction of data transfer in accordance with the SDA, the control data is read by the SDA Slave, when writing data controlled by the Master SDA. When 8-bit data transfer is completed, the opposite SDA control acknowledge bit or bits of the data transfer acknowledge bit NO.
2, the start bit "Start" and stop bits "Stop", can only be issued by the Master.
3, after completion of the transfer address 8, the address is successfully configured Slave devices must be transmitted "ACK". After a certain time Master or otherwise treated as overtime, will give up the data transfer, sending "Stop".
4, when the write data, Master transmit complete each eight data bits, if there is a space under the Slave device accepts a byte should answer "ACK", Slave device if there is no space to receive more bytes should answer "NACK" , Master did not receive any data will be treated as time expires to give up Master data transfer, sending "Stop" when after the receipt of "NACK" or a certain time.
5, when reading data, each Slave device 8 data bits have been sent, if the Master wishes to continue to read the next byte, Master should answer "ACK" to prepare for the next data prompt Slave, Master undesirable if read more byte, Master should answer "NACK" to prompt the Slave device is ready to receive Stop signals.
6, when the end time to Master Slave processing speed is too fast, Slave device may hold down the SCL (SCL = 0 to "line" occurs) to prevent the Master to send more data. At this time, as the case may be slowed or Master data transfer is completed.
In the case of actual application, data is not a mandatory requirement and the receiver must respond to the 8-bit data transmission, especially in the Master and Slave terminal GPIO are achieved by a method of software simulation, the programmer can be agreed in advance data transmission length, slave does not check NACK, sometimes helps reduce the effect of overhead. But if the party is a slave i2c hardware requirements must be standard NACK, master GPIO software simulation i2c party is not right to send NACK, there will be "slave receive stop" lead i2c hanging dead.
Under normal circumstances, I2C bus protocol to ensure normal read and write bus operation.
However, when the abnormality I2C master reset (watchdog operation, chip-board power supply abnormality cause a reset operation, a manual reset button, etc.) may lead to the I2C bus deadlock.
The following detailed description of the reasons bus Deadlock.
During read and write operations in I2C master device. After the master start signal to generate eight clock pulses SCL, and then pulls the SCL signal is low at this time, a response signal output from the device, the SDA signal is pulled low.
If this time the master device error reset, SCL will be released at a high level.
At this time, if the device is not reset, it will continue I2C response, the SDA has been pulled low until SCL goes low before the end of the response signal.
As for the I2C master is. After the reset detection signals SDA and SCL, SDA signal is low if it is found, that will be occupied by the I2C bus, it waits SCL and SDA signal goes high.
Thus, I2C master device waits to release the SDA signal from the device while waiting for another slave I2C master device to release the SCL signal low response signal, both wait for each other, into Deadlock I2C bus state.
Similarly, when the I2C read operation, the output data from the I2C device answers, if at this time the I2C master abnormal resetting the I2C data bit from the device output is exactly 0, will lead to a deadlock state I2C bus.
The method of
I2C try to use with reset input from the device.
All connections from the power supply I2C devices together, the tube is connected to the mains power supply MOS, and the MOS transistor is turned off is achieved by a master I2C.
From equipment design watchdog function in I2C.
Increase in the recovery program I2C I2C bus master device.
Method I2C master device after each reset, if it is detected the data line SDA is pulled low, the control of the I2C clock line SCL to generate clock pulses 9 (for the case of 8-bit data "9 clk can activate the" from NXP documents, NXP (Philips) as the originator of the I2C bus, that argument is credible), so I2C, recovering from device to complete the read operation from the suspended state of deadlock over.
This method has significant limitations, since most of a main apparatus built I2C module implemented by a hardware circuit, software is not able to directly produce the desired analog control signal SCL clock pulses.
Alternatively, the transmission conditions allow release I2C_Stop bus slave. If analog GPIO I2C bus is implemented, then the I2C operation before adding the I2C bus state detector I2C_Probe, if the bus is occupied, it can attempt to recover the bus, until the bus is released before proceeding. To ensure the integrity of the smallest I2C operating unit, not other events (interrupts, high-priority thread, etc.) interrupted.
Adding an additional bus on the I2C bus recovery equipment. This device monitors the I2C bus. When the device detects SDA is pulled low signal exceeds the specified time, the ninth clock pulse is generated on the SCL bus, of the I2C slave read operation, the recovery from a deadlock state. Recovery device having a bus requires programming, this function can be implemented in general MCU or CPLD.
On I2C I2C string into a buffer deadlock has recovered, as LTC4307 Linear's I2C bus is a bidirectional buffer, and has a function to restore the I2C bus deadlock. LTC4307 bus master devices connected to the input side, an output side connected to a bus from all devices. When the detected output side LTC4307 SDA or SCL signal is pulled low 30ms, automatically disconnect the I2C bus is connected to the input and output sides. 16 and generating clock pulses on the output side of the SCL signal to release the bus. When the bus successful recovery, the LTC4307 will again connect the input and output side of the bus to work properly.
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