IC design flow

1. Language: VHDL / verilog HDL

2. The phases of a typical software introduced:
input tools: Summit Summit Company
simulation tools: VCS, VSS Synopsys Company
synthesizer: DesignCompile, BC Compile Synopsys company
placement and routing tools: Preview companies and Silicon Ensemble Cadence
layout verification tool: Dracula, Diva Cadence company
static timing analysis: Prime Time Synopsys company
test: DFT Compile Synopsys company

3. Process
First stage: project planning
form a Project Mandate (progress of the project cycle management, etc.). Process: [market demand - research - Feasibility Study - Demonstration - Decision - the mission statement].

The second stage: overall design
to determine the design goals and, to further clarify the function of the chip, internal and external performance requirements, parameter index, demonstrate various possible options, select the best mode, processors, technology standards. Process: [Requirement Analysis - System Solutions - System Design - System Simulation].

Third stage: the detailed design and design for testability
secondary functions implemented to determine the structure of each module algorithm to determine the required resources needed to design chips, speed, power, bandwidth, gain, noise, load capacity, and the working temperature the time, cost-effective asked to select processing manufacturer, implementations, (full custom, semi-custom, ASIC, FPGA, etc.); testability design and timing analysis at once integrated in the detailed design, the design for testability is often based on need
FullScan, PartScan etc., include design for testability logic unit with the scan chain, the ATPG, and the boundary scan circuit BoundScan, the test Memory BIST. Process: [Logic Design - Decomposition functions - Details timing diagram - Block Logic Simulation - Circuit Design (behavioral algorithms, RTL level description) - Simulation function - Integrated (plus timing constraints and design library) - netlist - netlist simulation].

Phase IV: timing verification and layout
static timing analysis to extract all of the timing paths from the entire circuit, and then by calculating a path along the propagation delay on the signal, identify the timing constraints violation errors (mainly SetupTime and HoldTime), and motivation has nothing to do. In deep sub-micron processes, because the circuit is greater than the delay unit delays the connection, usually repeated more pre-layout, layout adjustment program several times, with a significance of layout. Process: [Pre-placement and routing (SDF file) - netlist simulation (with delay file) - Static Timing Analysis - layout - extraction --SDF file - after simulation - static timing analysis - Testing vector generation]

Fifth stage: processing and complete
process: [Design and production - chip testing - chip applications]

2, implementation;     

IC from the production object can be divided into a general purpose IC (such as CPU, DRAM, interface chips, etc.) and ASIC (Application Specific Integreted Circuit) two kinds, ASIC in response to a special purpose IC produced.

      From the structure can be divided into a digital IC, an analog IC, hybrid IC die number three, and SOC (system on chip) becomes the direction. From an implementation perspective it can be divided into three types. Based transistor stage, all the devices and interconnects layout are referred to as full-custom artificial (full-custom) design, this method is more suitable for mass production, requiring high integration, high speed, small size, low power consumption general-purpose IC or ASIC. Gate array (Gate-Array) unit and a standard (Standard-Cell) The semi-custom design (Semi-custom) basis due to their low cost, short cycle, low utilization of the chip and adapted to low-volume, requires the introduction of fast chips. Based on IC manufacturers have packaged PLD (Programmable Logical Design) design of the chip, because of its ease of use, "rewritable" of an integrated circuit by an integrated process not know the user's system welcome. His most important feature is simply to understand hardware description language you can use special EDA tools, "write" chip functions. But low PLD integration, slow, low utilization of the shortcomings of the chip so that he is only suitable for the new product prototype and small batch. In recent years, the PLD development was undoubtedly the most active FPGA (Field Programmable Gate Array) devices.

      From the process employed can be divided into a bipolar (bipolar), MOS, and other special process. Silicon (Si) semiconductor process based bipolar devices due to the large power consumption, a relatively low degree of integration in recent years with the rapid development of deep sub-micron to submicron technology, the speed of the MOS transistor is not an edge, and thus quickly It is high integration, low power consumption, noise immunity replaced by MOS transistors. MOS can be divided into NMOS, PMOS and CMOS three kinds; the development of CMOS process which is already very mature, occupy most of the market share of IC. AsGa device because of its high frequency range (which may be easily done at 0.35um 10GHz) is widely used as a microwave IC in which the special process has also been extensive studies. Although the art is applied to video acquisition also uses the same CCD sensor IC planar process, but its implementation and the standard semiconductor process are very different.

      From the design method can be divided into top-down (top-down) and the bottom-up methods. top-down design methodology

      in IC development, depending on the project requirements, according to the project funding and available for use EDA tools and human resources, according to the actual foundry processes, using different implementations is very important decision. ( 5) closely follow the trend of technological innovation and the company is the fundamental guarantee IC virtuous circle; (need to talk about it)?

   3, IC design EDA tools used;

      the saying goes, "For the public good work must first sharpen his tools."

      Improving IC design EDA tools has enabled engineers to completely get rid of the ignorance of the original manual operation. IC design EDA tools and always is a combination of the human brain. With the IC to keep the high level of integration, high speed, low power, high performance development, there is no high-reliability computer-aided design tools, it is impossible to complete the design.

      IC design EDA tools really started in the 1980s, the birth of the first workstation platform apollo 1983 years; 20 years of development, language (or graphical input tool) from the hardware description to logic simulation tool (LOGIC SIMULICATION), from logic synthesis (logic synthesis) to the automatic placement and routing (auto plane & route) system; physical detection rule (DRC & ERC) and extraction (LVS) to a final test chip; modern EDA tools covering almost all aspects of IC design.

      EDA tools mention IC design companies cadence can not say that with the collapse of the compass, it has become a veritable industry "boss" cadence provides almost all the tools IC design involved; but its tools and its reputation the same worthless! The rapid development of modern IC technologies set off a merger, reorganization boom in EDA software manufacturers.

      In addition to CADENCE company, more well-known companies, including mentor, avanti, synopsys and INVOEDA; mentor and cadence as a design at all levels of the company are development tools, simulation tools and AVANTI its HSPICE famous, SYNOPSYS is because the logic achievements and recognition as an integrated aspect of the market.

      Let's talk about the different stages of the tools and the design hierarchy;

      (1) input means (design input): for (TOP-DOWN) top-down design methodology, and often the first use of VHDL or VERILOG HDL to complete the device functional description, representative language input tools SUMMIT company VISUAL HDL and MENTOR's RENIOR and so on. Although many manufacturers (mostly FPGA vendors) offer their own proprietary hardware description language input, such as AHDL ALTRA companies, but all companies provide support for the IEEE standard VHDL, VERILOGHDL of.

      Design of the bottom, from the general pattern, or substantially gate input transistor begins, such tools typically have a cadence companies composer; viewlogic's viewdraw the like, and can be generated depending on the input transistor manufacturers or libraries the corresponding analog gate circuit netlist.

      (2) circuit simulation software (circuit simulation) :( divided into two categories of digital and analog).

     The key lies in the circuit simulation tool transistors physical model, the model and the actual physical characteristics of the most cutting process inevitably transistor operation waveforms obtained and more in line with the actual circuit, with the increasing degree of integration of the IC, increasingly narrow line width, transistor the models are becoming increasingly complex. Any circuit emulation libraries are based on a certain manufacturer, the manufacturer of these libraries are provided corresponding process parameters of the designer; as TSMC0.18um Cu CMOS process parameters up to as many as 300;

      can be used for digital simulation there are a lot of tools, advance logic simulation purposes only in order to verify the functional description is correct. For verilog HDL netlist generated, cadence verilog-XL is the company's most prestigious UNIX-based workstation simulation tools; and in recent years with the emergence of PC workstations, viewlogic the VCS and mentor's modelsim for its ease of use and rapid rise and became a rising star in the digital simulation tools based on cheap PC workstation; for VHDL netlist simulation, cadence companies LEAFROG; SYNOPSYS company VSS, while the mentor company based MODELSIM PC is become more and more newcomers are welcome.

      PSPICE originated in Berkley University, decades of development experience, with the transistor line widths continue to shrink, PSPICE also introduces more parameters and more complex transistor model. He remains one of the main tools in the analog circuit simulation submicron and deep submicron technology today. AVANTI is IC design automation software "young heroes", its HSPICE because of its excellent performance in the sub-micron and deep sub-micron processes has been widely used in recent years. cadence's spectre is simulation software, but applications far and wide PSPICE and HSPICE;

      for a particular process design, since not Si based bipolar or CMOS processes for their use, and thus have different design and simulation software; e.g. based AsGa process microwave devices used tool, better known as the HP eesoft the like;

     (3) synthesis tools (synthesis tools): FPGA and CPLD synthesis tool comprises a cadence of synplify; Synopsys's FPGAexpress and FPGA compiler; mentor's leonardo spectrum; in general different FPGA vendors offer special simulation and synthesis tools are suitable for their FPGA circuits, such as altera company MAXPLUS2 apply only its own MAX series chip; and the foundation was tailored XILINX devices ......

      The first IC tools should be integrated cadence of buildgates; and the latest version of Cadence Envisia Ambit (R) at 99 years of success in ASIC international company for 2.4 million design. Use of broader design compiler and also synopsys behavial compiler; design may be converted based on different libraries, logic synthesis tool to correspond to a certain process stage gate circuit means; Simulation of the door that are not the primary consideration in (gates delay ) Reversed-gate-level netlist to generate, the return circuit simulation stage and then simulated. The final simulation results netlist generated called physical netlist.

     (4) layout tools and automatic placement and routing (auto plane & route) tools cadence of the design framework is commonly based custom design a UNIX workstation layout software, and silicon ensemble, Envisia place & route DSM ; (cadence layout input tools Virtuoso)

     (. 5) physical verification (physical validate) and extraction (LVS) tool can still be divided into two categories ASIC and FPGA. ASIC design best known, is the most powerful of the cadence DRECULA, the layout process can be completed from the DRC (design rule check), the ERC (electrical characteristic test) to the LVS (parasitic extraction) once; the DIVA as a relatively weak software to provide more teaching purposes; AVANTI STAR-RC is a powerful tool for physical verification, and it is hercules LVS in recent years. As synthesis tool, like, FPGA vendor physical verification, and parasitic extraction to use more specialized software, and the simulation and synthesis tools integrated together. The MAXPLUS2 and the XILINX ALTERA FOUNDATION is typical;

     (6) Since VLSI especially pre-cast ULSI circuit chip costs are quite high (such as TSMC 0.25um CMOS process once the cost of pre-cast piece is 100 million dollars, while a pre-cast 0.18um Cu CMOS process as high as 3.3V 3 million dollars). Thus for ASIC chip, chip design requirements as accurately as possible. Preferably the complete elimination of errors; address power analysis; generating a special test circuit chip testing purposes; in response to this request, also had some special EDA tools, such as to perform power analysis, fault coverage analysis, test pattern generation and other purposes. Modern VLSI especially the rapid development of ULSI IC, it is relying on the progress of EDA tools in submicron and deep submicron process technology and the corresponding increase of the level. It should be said that there is no EDA tool would be no IC;

 

• VLSI ASIC design flow:

  1, the system described normalized (System Specification)
  comprises a system functionality, performance, physical size, pattern design, manufacturing process, design cycle, design costs and the like.
  2, functional design (Function Design)
  The implementation of the functions of the system designed. Usually is a data flow diagram between the sub-modules and each timing chart given system.
  3, logical design (Logic Design)
  This step is a functional configuration of the system. Typically text (Verilog HDL or VHDL), schematic, logic diagram showing the results of design, sometimes with Boolean expressions to represent the design results.
  4, circuit design (Circuit Design)
  circuit is designed to convert logic circuits designed to achieve expression.
  5, physical design (Physical Design or Layout Design)
  physical design or layout design is known as VLSI design is the most time-consuming step. It Circuit Design To each of components include transistors, resistors, capacitors, inductors, and integrated circuit fabrication layout information needed to convert the line between them.
  6, Design Verification (Design Verification)
  after the layout is complete, the work is a very important step layout verification. Including: Design Rule Check (DRC), a circuit layout extract (NE), an electrical inspection gauge (ERC) and the parasitic extraction (PE).
  =
  The IC level design method (top-down design example)
  system level functional level, RTL, gate-level, circuit level, layout level (physical level).

• (Copied appears from USTC BBS by wjcentury)
  ★ ★ digital circuit design tools
  classification product name Manufacturers
  logic synthesis, static timing analysis Blast RTL US company MAGMA

  VHDL / Verilog-HDL Simulator (simulation tool) Active-HDL from Aldec United States

  Mixed-language simulation NC-sim US company Cadence Design Systems
  Verilog simulator Verilog-XL ditto
  System C simulator NC- System C above
  VHDL simulator NC- VHDL above
  physical synthesis tool PKS Ibid
  super synthesis tool (with optimized configuration function) BuildGates Extreme Ibid.

  Simulation Verilog / VHDL compiler VCS / Scirocco American Synopsys'
  RTL-level logic synthesis tools from Synopsys DC expert US
  Vhdl / Verilog mixed design specifications and grammar checker company Synopsys LEDA United States

  U.S. FPGA synthesizer Synplify PRO Synplicity's
  physical synthesis Amplify U.S. Synplicity,
  testing and prototyping, Synplicity Certify SC USA

  VHDL / Verilog-HDL simulation tool from Mentor Graphics ModelSim US

  Verilog-HDL simulation tool TauSim American Tau Simulation Company
  Hardware Accelerator ARES US IKOS Systems Company
  Static Timming analytical tools EinsTimer United States, IBM

  Logic Simulator (Simulation) Explore the United States Aptix company
  Xcite American Axis Systems Company
  VirtuaLogic US IKOS Systems company
  VIVACE United States Mentor Graphics Corporation

  Analytical Power / optimization tool (RTL) WattSmith U.S. company Sente
  logic verification tools (ATPG) Specman Elite U.S. Verisity Design Company

  CODE · COVERAGE tools, tool Verification state COVERAGE US Trans
  EDA company
  Navigator / State US companies TransEDA

  Navigator American companies TransEDA

  Formal · Verifier (equivalence assessment) BoolesEye United States, IBM
  Tuxedo US Verplex Systems Company

  HDL debugging tools Debussy American Novas Software Company
  circuits synthesis tools, behavioral synthesis tools (VHDL programming) BooleDozer United States, IBM

  High Level circuit synthesis tool eXplorations Tools US Explorations company
  RTL design TeraForm US Tera Systems Company
  --------------------------------- -----

  ★ analog / digital-analog mixed-signal circuit design tools ★
  Category Name Manufacturer
  Analog Circuit Simulator (simulation tool) T-Spice Pro US Tanner Research Corporation

  SmartSpice US Silvaco International Company
  Eldo American company Mentor Graphics
  circuit diagram simulation / physical design environment COSMOS SE / LE Synopsys, Inc. USA

  Digital / analog mixed-signal simulation HSPICE / NanoSim US Synopsys'
  mixed-signal · Simulator (simulation tool) ICAP / 4 US intusoft company

  Mixed-signal · Simulator (simulation tool) US Graphi Mentor
  cs company
  RF Circuit Simulator (simulation tool) ADVance, CommLib United States Mentor Graphics Corporation
  Analog Macro Library USA Mentor Graphics Corporation

  Static Noise Analysis Tool (mixed-signal) SeismIC US CadMOS Design Technology Company

  Model Generator (analog) NeoCell US company Neolinear

  Analog circuit design tool MyAnalog Station USA company MyCAD

  Circuit simulation tool Star-Hspice US company Avanti
  Star-Sim US company Avanti

  Star-Time US company Avanti

  U.S. schematic editor Scholar Silvaco International Corporation
  S-edit US TANNER Company

  Analog, RF and mixed-signal simulation Cadence Analog Design Environment of Cadence US

  Hierarchical schematic capture tools from Cadence Virtuoso Composer American
  schematic entry Orcad Capture CIS, USA, Cadence
  Concept HDL Capture CIS, the United States Cadence's
  schematic simulation Pspice NC Desktop US company Cadence
  ------------ ---------------------------
  -

  ★ Hard / Soft design tools ★ coordinate
  name product manufacturers Category
  Hard / Soft coordinated design tools Cierto VCC Environment Cadence US company
  ArchGen American CAE Plus Company
  eArchitect US Viewlogic Systems Company

  Hard / Soft coordination validation tools SeamlessCVE United States Mentor Graphics Corporation
  ---------------------------------------
  -

  ★ ★ LSI Layout Design Tool
  Category Product Name Manufacturers

  Parasitic capacitance / impedance extraction tools DISCOVERY US Silvaco International Company

  IC layout design MyChip StationTM V6.4 US company MyCAD

  Parasitic capacitance / impedance parasitic extraction tool,
  the delay calculation tool SWIM / InterCal US Aspec Technology Company

  Parasitic capacitance / impedance extraction tools,
  circuit Simulator (simulation tool),
  Layout conversion tool Spicelink, Ansoftlinks US Ansoft Corporation

  Physical Layout Editor Virtuoso-XL Layout Editor US Cadence Design interactive object
  physical layout verification tool from Cadence Diva U.S.
  signal integrity timing analysis tools from Cadence U.S. SignalStorm

  Model Generator CLASSIC-SC US Cadabra Design Automation Company

  Layout Design Tool (with synthesis circuit) Blast Fusion U.S. Magma,

  Layout design tools DOLPHIN United States Monterey Design Systems company
  L-Edit Pro American Tanner Research Company
  MyChip Station US MyCAD company
  CELEBRITY, Expert US Silvaco International Company

  Phase Shift Mask design tools,
  the OPC design tools,
  Mask testing tools iN-Phase / TROPiC / CheckIt US Numerical Tecnologies company

  Layout parasitic extraction tool Star-RC US company Avanti
  logic simulation and layout design system 2000 Panda Chinese Mandarin
  ---------------------------- -----------
  -

  ★ ★ testing tool
  name manufacturers Category Product
  Test - Pattern conversion tool TDS iBlidge / SimValidator US Fluence Technology Company

  Test design tools TestBench United States, IBM
  TDX US Fluence Technology Company
  -------------------------------------- -
  -

  ★ ★ printed circuit board design tool
  classification product name Manufacturers

  Speed PCB design and verification SPECCTRAQuest US Cadence Design Systems Company
  PCB design configuration of the automatic wiring tool AllegroSPECCTRA US Cadence Design Systems Company

  Orcad Layout PCB design company Cadence Design Systems USA

  PCB PCB Thermal analysis tool temperature Ansoft Corporation U.S.
  welding temperature for a PCB analysis tool PCB SolderSim Ansoft Corporation U.S.
  PCB analysis tool with vibration and fatigue PCB Vibration Plus / PCB Fatigue Ansoft Corporation USA

  PCB / MCM extraction tools with the parasitic capacitance / impedance
  circuit Simulator (simulation tool) PCB / MCM Signal Integrity USA Ansoft Corporation

  Package (Package) design tools Advanced Packaging Designer / Ensemble US company Cadence

  Package (Package) Hybrid Thermal analysis tool temperature Ansoft Corporation U.S.
  package (Package) with a parasitic capacitance / impedance parasitic extraction tools Turbo Package Analyzer Ansoft Corporation USA

  PCB design tool ePlanner US Viewlogic Systems Company
  PCB design Protel DXP ALTIUM company

  ———————————————————————————————————————
  —

  ★ ★ other tools
  were classified product manufacturer
  AC / DC Design, analytical tools MotorExpert Korea jasontech company

  Technology · Simulator (simulation tool) ATHENA US Silvaco International Company

  Device · Simulator (simulation tool) ATLAS American Silvaco International Company

  Device simulation tool for process simulation tool Medici, Davinci, TSUPREM US company Avanti

  RF and microwave design ADS Agilent, USA
  The signal processing system-level design tools SPW4.8 US company Cadence Design Systems

  Digital signal processing and communications products system-level design tools Matlab / Simulink Mathworks, USA

  ———————————————————————————————————————
  —

  ★ ★ the PLD development system
  Classification Name Manufacturer
  programmable logic development tools MAXPLUS Ⅱ US ALTERA CORPORATION
  programmable logic circuit (including SOPC) development tools QUARTUS US ALTERA CORPORATION
  programmable logic development tools ISP expert / ispLEVER v3.0 U.S. Lattice the company

  Programmable logic development tools ISE 6.2i Foundation U.S. company Xinlinx
  programmable logic development tools Actel Designer R1-2003 US ACTEL Company

• In early 06 EDA market structure:
  (Cadence, Synopsys (02 merger Avanti), Mentor Graphics, FPGA's integrated synplify)
  market research firm Gartner Dataquest recently released a report on market trends EDA pointed out that before the emergence of a new leader in global EDA revenue growth will remain stagnant; and the new technology has the potential to dominate the company's current EDA market position changes.

  The report compiled by Gartner Dataquest EDA analyst Gary Smith, Daya Nadamuni, Laurie Balch and Nancy Wu, think of customers craving electronic system-level (ESL) tools, but lack the tools on the market. ESL tools lack is the report noted that "the only factor in the Register Transfer Level (RTL) tool to maintain sales growth."

  The report suggests that the EDA industry will eventually propose a practical ESL methodology, which is a critical first step toward ESL tool sales growth. Gartner Dataquest forecast, ESL tool market will reach 35.7% compound annual growth rate over the next five years, but the company hopes that this ratio would be even higher, "because the market needs explosive growth, so that the EDA world to pull out of the recession . "

  Gartner Dataquest to 65 nanometer and 45 nanometer design tools to predict long overdue, for example, EDA market fell about 0.6 percent in 2005, an estimated value of $ 3.96 billion. The market research firm predicted EDA revenue growth in 2006 to $ 4.27 billion in 2007, 4.65 billion in 2008, 5.15 billion in 2009 to $ 5.69 billion.

  The company expects, RTL tool market growth will exceed 9.8% in 2006 to nearly $ 1.4 billion. Predicted that, RTL in 2007, an increase of nearly $ 1.52 billion in 2008 to $ 1.64 billion, $ 1.78 billion in 2009, the overall CAGR of 7%. "Upon completion of the transfer of ESL, RTL market will shrink to zero-growth markets."

  The report notes that memory design group in a sense that ESL and design for manufacturability (DFM) challenges will be fully updated EDA market, the market dominant Cadence Design Systems, Synopsys and Mentor Graphics instead. "This is what we call an inflection point (inflection point)," the report said.

  This report decisively rejected the current existence of a "DFM market" argument. Instead, the report asserts, "DFM seems to be a generic term, similar to the verification, it contains multiple markets." The report believes that the best use of the term should be used as adjectives to describe a tool, such as the "DFM-aware router (DFM-aware router) ".

  Using the data for 2004, Gartner Dataquest also listed for each sub-category of market diversification EDA market share.

  MathWorks in 2004 ranked ESL design and simulation of the list, occupying 33% of the market. Synopsys won 26%, CoWare share of 19%. In 2003 28% share of Cadence in 2004 to 8% erosion.

  $ 263 million in logic synthesis market, Synopsys maintained 85 percent share of the dominant, the report says, and predicts the market will grow slowly but stable, reaching $ 291 million in 2006, $ 329 million in 2009.

  Magma Design Automation "win over" the first card IC implementation, as Cadence and Synopsys have exited the field. Custom layout and wiring market, Cadence stable operation of 72% of the market share, Mentor Graphics far behind at 10%. Gartner Dataquest predicts that the market will decline slightly in front of Yang's first growth in 2007.

  In the $ 167 billion in market design rule checking, Mentor Graphics share to 58%, significantly ahead of Cadence (25%) and Synopsys (15%). But the report points out, Mentor Graphics is facing strong competition from the two companies and the Magma, Magma claimed that Mentor Graphics' Calibre can not effectively deal with 65-nanometer design.

  In the resolution enhancement (RET) technology market, Synopsys 40% to 49% of the results beat Mentor Graphics. Since RET is increasingly important for the industry's ability to narrow line width, Gartner Dataquest believes that the market will grow rapidly.

  In the $ 270 million of PCB layout tools market, Mentor Graphics won 39% of the share, Cadence 29%, *** Zuken 18%. Gartner Dataquest outlook PCB design tool for growth situation is excellent.

  Synplicity the FPGA synthesis market continues to expand ahead of Mentor Graphics dominance, occupying 67% of the market, while only 26% of Mentor Graphics. However, the market will grow slowly.

• Mentor's product line:
  Real-time OS: Nucleus
  IC pulp black liquor and Design (IC Design tool chain):

  Design Capture
  Design Architect IC

  Simulation
  ADVance MS
  Mach TA
  Eldo
  Eldo RF
  ADVance MS RF

  Physical Layout
  IC Station SDL
  ICgraph Basic
  ICassemble
  HotPlot
  AutoCells

  Physical Verification
  Calibre DRC
  Calibre LVS
  Calibre DESIGNrev
  Calibre Interactive
  Calibre RVE

  Parasitic Extraction
  Calibre xRC
  Calibre xL
  Calibre LVS

  Litho Modeling
  Calibre OPCverify
  Calibre RET (OPC and PSM)

  Mask Data Preparation
  Calibre MDP

  Design for Manufacturing
  Calibre YieldAnalyzer
  Calibre YieldEnhancer
  YieldAssist
  Calibre LFD: Litho-Friendly Design
  ＝
  ＝
  Scalable Verification

  Assertion-Based Verification
  Questa AFV (Advanced Functional Verification)
  Questa SV (SystemVerilog)
  0-In® Assertion Synthesis
  0-In Formal Verification
  0-In® Clock-Domain Crossing (CDC)
  0-In® CheckerWare®

  Testbench Automation
  Questa AFV (Advanced Functional Verification)
  Questa SV (SystemVerilog)

  Coverage-Driven Verification
  Questa AFV (Advanced Functional Verification)
  Questa SV (SystemVerilog)
  0-In® Assertion Synthesis
  0-In Formal Verification
  0-In® CheckerWare®

  Verification IP
  0-In® CheckerWare®
  PCI Express Monitor
  Universal Serial Bus Monitor
  AMBA AXI Monitor
  Serial Attached SCSI Monitor
  Open Core Protocol Monitor
  10 Gigabit Ethernet Monitor

  Digital Simulation
  ModelSim® SE
  ModelSim® LE
  ModelSim® IN

  Analog/Mixed-Signal Simulation
  Advance MS
  ADVance MS RF

  Hardware/Software Co-Verification
  Seamless
  Seamless FPGA

  Emulation
  VStationPRO
  VStationTBX
  iSolve
  =
  =
  PCB Systems
  Board Station

  System Design
  I/O Designer
  Board Architect
  Design Architect
  Constraint Editor System

  Analysis & Verification
  HyperLynx
  ICX / TAU
  Quiet Expert
  AccuSim II

  Physical Design
  TeamPCB
  Board Station RE
  XtremePCB

  Data Management
  DMS

• IC Design:

  Capture Design (Verilog / Spice ...)
  the Simulation (Verilog / Spice, Modelsim supports interfaces)

  Physical Layout
  Physical Verification(DRC, LVS…)
  Parasitic Extraction(xRC,LVS…)

  Lotho Modelling
  Mask Data Preparation
  Design for Manufacturing