verilog modelsim memory 仿真笔记1

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ram_tb.v

`timescale 1ns/1ns

module ram_tb();
  
reg clk;
reg [7:0] addr;
wire [7:0] data;
  
ram ram1(
  .clk(clk),
  .addr(addr),
  .data(data)
);

initial
begin
  clk = 0;
  addr = 8'b00000000;
end

always #10 clk = ~clk;

always #40 addr = 8'b00000011;

always @(posedge clk)
begin
  addr = 8'b00000010;
end

endmodule

ram.v

module ram(
    input clk,
    input [7:0] addr,
    output reg [7:0] data
);

reg [7:0] mem[0:255];

initial
begin
  mem[0] = 8'b00000011;
  mem[1] = 8'b00001100;
  mem[2] = 8'b00110000;
  mem[3] = 8'b11000000;
  
//  $readmemh("file_name", mem_array, start_addr, stop_addr);
end

always @ (posedge clk)
begin
    data <= mem[addr];
end

endmodule