重温FPGA之警报防护系统设计 verilog实现

1.题目

2.源码

// *********************************************************************************
// Project Name : Alarm_system
// Email        : [email protected]
// Website      : https://home.cnblogs.com/u/hqz68/
// Create Time  : 2019/12/13 
// File Name    : Alarm_system.v
// Module Name  : Alarm_system
// Abstract     :
// editor		: sublime text 3
// *********************************************************************************
// Modification History:
// Date         By              Version                 Change Description
// -----------------------------------------------------------------------
// 2019/12/13    宏强子           1.0                     Original
//  
// *********************************************************************************
`timescale      1ns/1ns
module Alarm_system (
	//system signals
	input					sclk			, 		//10m
	input					s_rst_n			,
	//input
	input					sensor			,

	input 					start			,
	input 					relieve			,
	input 					test			,
	//output
	output	reg				warning			
);

//========================================================================\
// =========== Define Parameter and Internal signals =========== 
//========================================================================/
localparam			Relieve		=	3'b000;
localparam			Protect		=	3'b001;
localparam			Test		=	3'b010;

//localparam			time_5s	=	50_000_000;		//真实5s数字
localparam			time_5s	=	50_00;			//加快仿真使用

reg		[25:0]		time_cnt		;
reg					time_cnt_end	;

reg		[2:0]		state			;
//=============================================================================
//****************************     Main Code    *******************************
//=============================================================================
//状态机
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		state <= Relieve;
	else if (state == Relieve & start == 1)
	    state <= Protect;
	else if (state == Relieve & test == 1)
	    state <= Test;    
	else if (relieve == 1 )
	   state <= Relieve;        
	else	
       state <= state;
end

//一秒计数器
always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		time_cnt <= 24'd0;
	else if (time_cnt <= time_5s -1 & sensor == 1 & state == Protect)
		time_cnt <= time_cnt + 1'b1;
	else	
        time_cnt <= 24'd0;
end

//一秒标志    
always @ (posedge sclk or negedge s_rst_n) begin
    if(s_rst_n == 1'b0)
    	time_cnt_end <= 1'b0;
    else if (relieve == 1)
    	time_cnt_end <= 0;    
    else if (time_cnt == time_5s -2)
    	time_cnt_end <= 1'b1;
    else	
        time_cnt_end <= time_cnt_end;
    end

always @ (posedge sclk or negedge s_rst_n) begin
	if(s_rst_n == 1'b0)
		warning <= 1'b0;
	else if (time_cnt_end == 1'b1 | state == Test)
	    warning <= 1'b1;    
	else	
        warning <= 1'b0;
end


endmodule

3.测试平台

`timescale 1ns/1ns
module tb_sim();

reg			sclk		;
reg			s_rst_n		;

reg			sensor		;
reg			start		;
reg			relieve		;
reg			test		;


wire		warning 	;

initial	 begin
	sclk = 1;
	s_rst_n = 0;
	sensor	= 0;
	start	= 0;
	relieve	= 0;
	test	= 0;	
	#100
	s_rst_n = 1;

	#500
	start	= 1;
	#100
	start	= 0;

	// #100					//测试传感器时，将这部分注释取消
	// sensor	= 1;
	// #60000
	// sensor	= 0;

	#100
	relieve	= 1;
	#100
	relieve	= 0;

	#100
	test	= 1;
	#100
	test	= 0;

	#100
	test	= 1;
	#100
	test	= 0;

	#100
	relieve	= 1;
	#100
	relieve	= 0;
end

always #50 sclk = ~sclk;


Alarm_system 		Alarm_system_inst(
	//system signals
	.sclk				(sclk	 	), 		//10m
	.s_rst_n			(s_rst_n 	),
	//input
	.sensor				(sensor		),
	.start				(start		),
	.relieve			(relieve	),
	.test				(test		),
	//output
	.warning			(warning	)
);


endmodule

4.仿真波形

有警报器测试

整个状态跳转