FPGA随手记03

 1 module flow_led(
 2 input sys_clk , //系统时钟，外部时钟50M
 3 input sys_rst_n, //系统复位，低电平有效
 4 
 5 output reg [3:0] led //4个LED灯
 6 );
 7 
 8 //reg define
 9 reg [23:0] counter;
10 /*点灯如何实现？首先定义led4位寄存器，对应四个接口。灯接法共地，输出高电平(1)点亮一个
11 灯。
12  如何循环点亮灯?led <= 4'b0001;即 led[0]=1
13  led[1]=0
14  led[2]=0
15  led[3]=0
16 
17  执行一次{led[2:0],led[3]}取高位与低位拼接,得led<=4'b0010
18 
19 
20 延时如何实现？首先理解在FPGA的always块是并行执行，但是
21 在always中是顺序执行,即counter == 24'd1000_0000时(24位十进制数)
22  counter <= 24'd0;
23 
24  led[3:0] <= {led[2:0],led[3]};
25 
26 
27  */
28  //*****************************************************
29  //**                     main code
30  //*****************************************************
31 
32  //计数器对系统时钟计数，计时0.2秒
33  /*
34  t=1/f=1/50,000,000
35  0.2s=t*10000,00000
36  
37  */
38  always @(posedge sys_clk or negedge sys_rst_n) begin
39  if (!sys_rst_n)
40  counter <= 24'd0;
41  else if (counter < 24'd1000_0000)
42  counter <= counter + 1'b1;
43  else
44  counter <= 24'd0;
45  end
46 
47  //通过移位寄存器控制IO口的高低电平，从而改变LED的显示状态
48  always @(posedge sys_clk or negedge sys_rst_n) begin
49  if (!sys_rst_n)
50  led <= 4'b0001;
51  else if(counter == 24'd1000_0000)
52  led[3:0] <= {led[2:0],led[3]};
53  else
54  led <= led;
55  end
56 
57  endmodule