This section provides designers with the data sheet specifications for Cyclone®devices. The chapters contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information,DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Cyclone devices.
这一部分为设计者介绍了cyclone器件家族的特性。本章包含内部结构信息、配置、JTAG边界扫描测试信息、DC工作条件、AC时序特点、功耗指南和cyclone器件的订阅信息。
chapter1 Introduction
The Cyclone®field programmable gate array family is based on a 1.5-V,0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase-locked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, Cyclone devices are a cost-effective solution for data-path applications. Cyclone devices support various I/O standards, including LVDS at data rates up to 640 megabits per second (Mbps), and 66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices. Altera also offers new low-cost serial configuration devices to configure Cyclone devices.
Cyclone®现场可编程门阵列系列基于1.5 V，0.13-μm，全铜铜SRAM工艺，密度高达20,060个逻辑元件（LE）和高达288 Kb的RAM。 有功能像用于时钟的锁相环（PLL）和专用双倍数据速率（DDR）接口，以满足DDR SDRAM和快速周期RAM（FCRAM）内存要求，Cyclone器件在数据路径应用上是一种经济高效的解决方案。 Cyclone设备支持各种I / O标准，包括数据速率高达640兆比特每秒（Mbps）的LVDS，以及66-和33-MHz，64-和32-位周边组件互连（PCI），用于与ASSP和ASIC设备进行接口和支持。 Altera也提供新的低成本串行配置设备来配置Cyclone设备。
Cyclone®现场可编程门阵列系列基于1.5 V，0.13-μm，全铜铜SRAM工艺，密度高达20,060个逻辑元件（LE）和高达288 Kb的RAM。 有功能像用于时钟的锁相环（PLL）和专用双倍数据速率（DDR）接口，以满足DDR SDRAM和快速周期RAM（FCRAM）内存要求，Cyclone器件在数据路径应用上是一种经济高效的解决方案。 Cyclone设备支持各种I / O标准，包括数据速率高达640兆比特每秒（Mbps）的LVDS，以及66-和33-MHz，64-和32-位周边组件互连（PCI），用于与ASSP和ASIC设备进行接口和支持。 Altera也提供新的低成本串行配置设备来配置Cyclone设备。
The Cyclone device family offers the following features:
■ 2,910 to 20,060 LEs, see Table 1–1 ***2,910至20,060 逻辑单元，见表1-1
■ Up to 294,912 RAM bits (36,864 bytes) ***最多294,912个RAM位（36,864字节）
■ Supports configuration through low-cost serial configuration device ***通过低成本串行配置设备支持配置
■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ***支持LVTTL，LVCMOS，SSTL-2和SSTL-3 I / O标准
■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ***支持66和33-MHz，64位和32位PCI标准
■ High-speed (640 Mbps) LVDS I/O support ***高速（640 Mbps）LVDS I / O支持
■ Low-speed (311 Mbps) LVDS I/O support ***支持低速（311 Mbps）LVDS I / O
■ 311-Mbps RSDS I/O support ***311-Mbps RSDS I / O支持
■ Up to two PLLs per device provide clock multiplication and phase shifting ***每个器件最多两个PLL提供时钟倍增和相位偏移
■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ***最多八个全球时钟线，每个可用六个时钟资源逻辑阵列块（LAB）行
■ Support for external memory, including DDR SDRAM (133 MHz),FCRAM, and single data rate (SDR) SDRAM
■ 2,910 to 20,060 LEs, see Table 1–1 ***2,910至20,060 逻辑单元，见表1-1
■ Up to 294,912 RAM bits (36,864 bytes) ***最多294,912个RAM位（36,864字节）
■ Supports configuration through low-cost serial configuration device ***通过低成本串行配置设备支持配置
■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards ***支持LVTTL，LVCMOS，SSTL-2和SSTL-3 I / O标准
■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard ***支持66和33-MHz，64位和32位PCI标准
■ High-speed (640 Mbps) LVDS I/O support ***高速（640 Mbps）LVDS I / O支持
■ Low-speed (311 Mbps) LVDS I/O support ***支持低速（311 Mbps）LVDS I / O
■ 311-Mbps RSDS I/O support ***311-Mbps RSDS I / O支持
■ Up to two PLLs per device provide clock multiplication and phase shifting ***每个器件最多两个PLL提供时钟倍增和相位偏移
■ Up to eight global clock lines with six clock resources available per logic array block (LAB) row ***最多八个全球时钟线，每个可用六个时钟资源逻辑阵列块（LAB）行
■ Support for external memory, including DDR SDRAM (133 MHz),FCRAM, and single data rate (SDR) SDRAM
支持外部存储器，包括DDR SDRAM（133 MHz），FCRAM和单数据速率（SDR）SDRAM
■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.
■ Support for multiple intellectual property (IP) cores, including Altera® MegaCore® functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.
支持多种知识产权（IP）核心，包括Altera®MegaCore®功能和Altera Megafunctions合作伙伴程序（AMPPSM）宏功能。
Notes to Table 1–2:
(1)Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package).
(1)Cyclone devices support vertical migration within the same package (i.e., designers can migrate between the EP1C3 device in the 144-pin TQFP package and the EP1C6 device in the same package).
Cyclone器件支持同一封装内的垂直迁移（即设计人员可以对144引脚TQFP封装的EP1C3器件和EP1C6器件进行垂直迁移）
a、Vertical migration means you can migrate a design from one device to another that has the same dedicated pins, JTAG pins, and power pins, and are subsets or supersets for a given package across device densities. The largest density in any package has the highest number of power pins; you must use the layout for the largest planned density in a package to provide the necessary power pins for migration.
垂直迁移意味着您可以将设计从一个设备迁移到另一个具有相同的专用引脚，JTAG引脚和电源引脚，以及是针对设备密度的给定包的子集或超集。该任何封装中最大密度的电源引脚数量最多; 您必须在封装中使用最大计划密度的布局为迁移提供必要的电源引脚。
b、For I/O pin migration across densities, cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins can be migrated. The Quartus® II software can automatically cross-reference and place all pins for you when given a device migration list. If one device has power or ground pins, but these same pins are user I/O on a different device that is in the migration path,the Quartus II software ensures the pins are not used as user I/O in the Quartus II software. Ensure that these pins are connected to the appropriate plane on the board. The Quartus II software reserves I/O pins as power pins as necessary for layout with the larger densities in the same package having more power pins
对于跨密度的I / O引脚迁移，
交叉引用可用的I / O针对给定封装的所有计划密度使用器件引脚输出以确定哪些I / O引脚可以迁移。 当给定设备迁移列表后，Quartus®II软件可以自动交叉引用并放置所有引脚。 如果一个设备有电源或接地引脚，但这些相同的引脚在不同的设备上却是用户I / O，这就是一个迁移路径，Quartus II软件确保引脚不被用作Quartus II软件中的用户I / O。 确保这些引脚连接到电路板上的相应网络。 Quartus II软件保留I / O引脚作为功率引脚，特别针对具有较大密度的且在同一个封装中有更多的电源引脚的器件布局中。
