十进制计数器和BCD七段译码数码管显示的VHDL实现

十进制计数器和BCD七段译码数码管显示的VHDL实现

library ieee;
use ieee.std_logic_1164.all;
entity counter is
port
(
	a:in std_logic_vector(3 downto 0);
	hex:out std_logic_vector(6 downto 0)
);
end counter;

architecture one of counter is
begin
	process(a)
	begin
		 case a is
			 when "0000"=>hex<="1000000";
			 when "0001"=>hex<="1111001";
			 when "0010"=>hex<="0100100";
			 when "0011"=>hex<="0110000";
			 when "0100"=>hex<="0011001";
			 when "0101"=>hex<="0010010";
			 when "0110"=>hex<="0000010";
			 when "0111"=>hex<="1111000";
			 when "1000"=>hex<="0000000";
			 when "1001"=>hex<="0010000";
			 when others=>hex<="1111111";
		 end case;
	end process;
end ;
library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is
	port
	(
		clk,res,set: in std_logic;
		d:in std_logic_vector(3 downto 0);
		q: out std_logic_vector(6 downto 0);
                    cout:out std_logic
	);
end counter;

architecture one of counter is
	component display 
	port 
	( 
                a:in std_logic_vector(3 downto 0);
                hex:out std_logic_vector(6 downto 0)
  	);
	end component;	
	signal temp:std_logic_vector(3 downto 0);	
begin	
inst1 : display port map 
                   (
		a => temp,
		hex => q
	          );	
	process(clk,res,set) 
	begin 
	if (res='0') then
	temp<="0000";
	elsif(clk'event and clk='1') then	
	 if(set='0') then
	 temp<=d;
	 elsif
       temp="1001"then
		temp<="0000";
		else
       temp<=temp+1;		
	end if;	
    end if;
  end process;
cout<='1'when temp="1001"else'0';
end ;