1. Door-level modeling syntax
1. Module definition
module 模块名(端口名1 ,端口名2 ,...);
...
endmodule
例:
module MUX4x1(Y,A,B,C,D,S1,S0,EN_);
Identifiers in Verilog HDL language are composed of letters, numbers, dollar signs, and underscores. Letters are case-sensitive, and the beginning of an identifier can only be letters or underscores.
2. Port statement
Verilog HDL keywords | Port type |
---|---|
input | Input port |
output | Output port |
inout | Bidirectional port |
The port defaults to 1 bit width, that is, only 1 bit of valid information can be transmitted
端口类型 [端口位宽左界:端口位宽右界] 端口名;
例如:
input [2:0] cin;
outout[0:4] cout;
inout [4:7] fast;
In the port declaration, the defined port declaration bit is wire type by default; except that output can be defined as reg type, input and inout can only be wire type.
3. Door-level call`
逻辑门类型 <实例名称(可选)> (端口连接)
例:
not (s1_n , s1);
buf b1 (out1 , in);
Logic gates are divided into two categories:
buf (buffer), not (not gate)
single-input logic gate function table,
multi-input logic gate,
multi-input call
and(Y,A,B);
or (Y,A,B);
and and1 (Y,A,B);
4. Module instantiation
模块名称 实例名称 (端口连接)
例
MUX4*1 mymux(.Y(y), .A(a), .B(b), .C(c), .D(d), .En(e), .S1(f), .S0(g));
5. Internal connection statement
wire [线宽-1 :0] 线名称;
例:
wire [3:0] b; //定义4位网线b
wire a; //定义1位网线a
2. Typical gate-level modeling
1. Four-bit full adder
Four-bit full adder is composed of 1-bit full adders in series
The RTL diagram of a 1-bit full adder is shown in the figure below
module fulladd(cin ,A ,B ,S ,cout);
output S,cout;
input cin ,A ,B;
xor (S, cin , A , B);
and (a1, cin , A);
and (a2, cin , B);
and (a3, A , B);
or (cout , a1 , a2 , a3);
endmodule
The RTL diagram of the four-bit full adder is shown in the figure below
module add4 (S, COUT , CIN , A , B);
output [3:0] S;
output COUT;
input [3:0] CIN, A, B;
wire c0 ,c1 ,c2;
fulladd add0(.S(S[0]) , .cout(c0) , .cin(CIN), .A(A[0]), .B(B[0]));
fulladd add1(.S(S[1]) , .cout(c1) , .cin(c0), .A(A[1]), .B(B[1]));
fulladd add2(.S(S[2]) , .cout(c2) , .cin(c1), .A(A[2]), .B(B[2]));
fulladd add3(.S(S[3]) , .cout(COUT) , .cin(c2), .A(A[3]), .B(B[3]));
endmodule
The simulation results are shown in the figure below;
2.
2-4 decoder gate-level circuit 2-4 decoder is to input 00 01 10 11, respectively output four different values.
The RTL circuit diagram is shown below:
module DEC2_4(A,B,En,Z);
input A,B,En;
output [3:0] Z;
wire n1,n2;
not (n1, A);
not (n2, B);
nand(Z[0],n1,n2,En);
nand(Z[1],n1,B,En);
nand(Z[2],A,n2,En);
nand(Z[3],A,B,En);
endmodule
The simulation results are shown in the following figure
3. Master-slave D flip-flop
D flip-flop is a memory with memory function and zero stable state storage.
Function table
Timing diagram
RTL gate-level circuit diagram as shown below:
module MSDFF(D,Q,Qbar,C);
output Q,Qbar;
input D,C;
not
not1(NotD, D),
not2(NotC, C),
not3(NotY, Y);
nand
nand1(D1,D,C),
nand2(D2,C,NotD),
nand3(Y,D1,Ybar),
nand4(Ybar,D2,Y),
nand5(Y1,Y,NotC),
nand6(Y2,NotY,NotC),
nand7(Q,Qbar,Y1),
nand8(Qbar,Y2,Q);
endmodule
The simulation circuit diagram is shown in the following figure.
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