1. FPGA (Fild Programmable Gate Array), namely Field Programmable Gate Array, is based on PAL, GAL, and CPLD programmable devices based on further development products.
Features of FPGA:
1. FPGA is a kind of customized semiconductor circuit in the field of application-specific integrated circuit (ASIC: a circuit design that is highly integrated but cannot be modified after completion). It not only solves the deficiencies of customized circuits, but also provides customer service for the original The shortcomings of the limited number of gate circuits of the programming device;
2. Working method: the working method of the lookup table;
3. The programming language is executed in parallel with high execution efficiency;
4. Programming language: Verilog HDL/VHDL;
5. FPGA contains a large number of IP Nuclear, convenient for development.
The type of FPGA:
Xilinx (Xilinx)
Altera (Altera, now acquired by Intel)
Lattice (Lattice)
Microsemi (Microsemi)
Introduction to the internal units of FPGA 
Programmable IO unit: It can realize different circuit characteristic designs, such as pull-up and pull-down resistance, drive current, etc.;
Programmable logic unit: It can flexibly change its internal connection configuration according to the design, so as to complete different logic functions ( Main method: lookup table);
low-level embedded unit: mainly refers to some functional modes, DSP phase-locked loop, etc.;
embedded block RAM: can be configured as RAM, ROM and other commonly used storage modules.
Wiring resources: The length of the connection and the industry will affect the driving capability and transmission speed of the signal.
Hard core: DDR3\DDR2, etc., used to drive peripherals.
2. FPGA development process
Design input: schematic diagram or programming language;
RTL simulation: functional simulation;
design synthesis: translate the language into "and", "and or"," or ". "Not" and other languages and output the logic netlist;
layout and routing: different layout and routing will have a great impact on program operation;
gate-level simulation: including gate delay and layout delay, which can better reflect The actual working condition of the chip;
timing analysis: check whether the engineering comfort meets the design requirements.
Disclaimer: This article is only suitable for learning, and its content contains excerpts and summaries from the book. Welcome everyone to add and make progress together.