#Zhizhiqiongli, study the ancients; Li Deliyan, no questions about the west and east.
I have recently done something about Robei, and the progress is not good at all. The display image exported by sobel edge detection is simply killing me. Near the end of the term, there are a lot of course reports to write, and I feel exhausted. I always want to give up the game, but I'm not willing to stop here, so keep going!
The content of this blog happened to be someone else asked me a question. When I thought it was a good blog material, I took it out and wrote it. (Now blogging is simply my only motivation to stick to the game)
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Robei EDA has a problem, that is, all the code is directly open source, so that the display is clear, but there is also a problem, it is impossible to call the IP core, maybe the general digital IP can be described by Verilog , But PLL is different. Due to the particularity of PLL, it cannot be directly described in Verilog, so how to make the code have IP during actual programming without affecting the original structure of the code synthesized by Robei.
My idea is to generate a fake PLL module in Robei EDA, encapsulate the IO for it, but keep the code writing part, and then use it as a normal IO to connect the entire code at a level, and finally Generate Verilog code and pin constraint files. Then, configure the PLL IP core for the imported Project on Vivado or Quartus. After configuring the IP, instantiate it on the fake clock module created in robei. In this way, an awkward and polite IP is configured.
The specific operation is as follows:
Take Quartus as an example here (why not Xilinx, because I write a blog in the dorm and the Vivado compilation on the notebook is too slow)