Introduction of vivado common IP

Transfer from: https://blog.csdn.net/yundanfengqing_nuc/article/details/108223603

Concat

The realization of this IP is the function of bit splicing, as shown in the figure below. Here, four 1-bit data are to be spliced ​​into one 4-bit data. Therefore, the Number of Ports is set to 4, and the bit width of the input port is set to 1.

Slice

The function of Slice is just the opposite of the function of Concat. The IP is to extract 1 or more bits from a multi-bit wide data, as shown in the figure below. The input data is 32 bits, and now the lower 4 bits are taken from it, so fill in 3 in the Din From column and 0 in the Din Down To column. At this time, the Dout Width will be automatically updated to 4.

Constant

The function of this IP is very simple, that is, output a fixed constant, and the bit width can be customized, as shown in the figure below. Here we need to output a 1-bit constant 0, so Const Width is set to 1, and Const Val is set to 0.

Utility Reduced Logic

This IP implements the bit reduction function. For example, for 8-bit data, the bit reduction and is the AND of each bit. As shown in the figure below, it can support AND, OR, XOR.

Utility Vector Logic

This IP implements bitwise logic operations, such as bitwise AND of two 8bit data, as shown in the figure below. Supports AND, OR, XOR, negation, etc. If you choose to invert, there is only one input port.

IBUFDS, IBUFGDS and OBUFDS

IBUFDS, IBUFGDS and OBUFDS are all differential signal buffers, used for buffering and conversion between interfaces of different levels. IBUFDS is used for differential input, OBUFDS is used for differential output, and IBUFGDS is a dedicated input buffer for clock signals.

The difference between IBUFDS and IBUFDS_GTE2 between BUFG and differential to single-ended

BUFG
BUFG converts a local clock to a global clock to reduce clock delay.

When IBUFDS
uses differential clock to single-ended, for ordinary banks, IBUFDS can be used.

IBUFDS_GTE2
For high-speed banks, you need to use IBUFDS_GTE2. If you still use IBUFDS, an error will be reported when compiling or generating bits, indicating that there is a problem with the clock constraint. The level of the normal differential clock does not need to be constrained. You can generate bits after constraining. But the transferred single-ended clock cannot be used.

IBUFDS_GTE2 primitives are as follows

 IBUFDS_GTE2 #(
     .CLKCM_CFG("TRUE"),   // Refer to Transceiver User Guide
     .CLKRCV_TRST("TRUE"), // Refer to Transceiver User Guide
     .CLKSWING_CFG(2'b11)  // Refer to Transceiver User Guide
  )
  IBUFDS_GTE2_inst (
     .O(clk_156_25M),         // 1-bit output: Refer to Transceiver User Guide
     .ODIV2(), // 1-bit output: Refer to Transceiver User Guide
     .CEB(1'b0),     // 1-bit input: Refer to Transceiver User Guide
     .I(Q0_CLK1_GTREFCLK_PAD_P_IN),         // 1-bit input: Refer to Transceiver User Guide
     .IB(Q0_CLK1_GTREFCLK_PAD_N_IN)        // 1-bit input: Refer to Transceiver User Guide
  );