Vivado IP core RAM Block Memery Generator
Table of contents
foreword
This time I will introduce the use of the RAM (Block Memery Generator) IP core in vivado , and I hope it will be helpful to everyone.
Tip: The following is the text of this article, all of which are original by the author himself. It is not easy to write an article. I hope you will attach a link to this article when reposting.
1. Configuration steps
Search for Block Memery Generator in vivado , and after finding the IP core, you can complete the corresponding configuration according to the following operations. This configuration is single port mode .
1. First configure the Basic interface, as shown in Figure 1.
2. Next, configure the Port A Options interface, as shown in Figure 2.
3. Then configure the Other Options interface, as shown in Figure 3. Here you can add an initialization file, that is, a coe file, to initialize the stored data.
4. Finally, there is a Summary interface, as shown in Figure 4, which does not require us to configure, it is just an introduction page.
After the above 4 interfaces are configured, click the OK button in the lower right corner to generate the IP core.
2. Simulation
1. Top-level code
Create a top-level module named ram_read to instantiate the IP core just generated.
code show as below:
`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/07/27 16:43:07
// Design Name:
// Module Name: ram_read
// Project Name:
// Target Devices:
// Tool Versions: 2017.4
// Description:
// Dependencies:
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//
//虽然是ram，本次将ram当rom使用
module ram_read(
input clk, //输入时钟信号
input rst_n, //输入复位信号
input start, //输入开始读信号
input [10 : 0] addr, //输入读地址
input [31 : 0] din, //本次用不到
output reg over, //输出读的数据有效信号
output reg [31 : 0] dout //输出读到的数据
);
//reg define
reg en; //读使能信号
reg we; //读写选择
reg [1:0] cnt; //计数器
//wire define
wire [31:0] data; //读的数据
always @(negedge clk or negedge rst_n)
begin
if(!rst_n)
cnt<=0;
else if( (start==1)&(cnt<3))
cnt<=cnt+1;
else
cnt<=0;
end
always @(negedge clk or negedge rst_n) //下降沿设定使能
begin
if(!rst_n)
begin en<=0;we<=0;end
else if(0<cnt<3)
begin en<=1;we<=0;end
else
begin en<=0;we<=0;end
end
always @(posedge clk or negedge rst_n) //上升沿读取稳定数据
begin
if(!rst_n)
begin over<=0;dout<=0;end
else if(cnt==3)
begin over<=1;dout<=data;end
else
begin over<=0;dout<=0;end
end
ram_sam_re_ip u1_ram_sam_re_ip ( //例化ram
.clka(clk), // input wire clka
.ena(en), // input wire ena
.wea(we), // input wire [0 : 0] wea
.addra(addr), // input wire [10 : 0] addra
.dina(din), // input wire [31 : 0] dina
.douta(data) // output wire [31 : 0] douta
);
endmodule
2. Simulation code
Create a simulation module named ram_read_tb , which is used to simulate the IP core instantiated by the top-level module just now.
code show as below:
`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/07/27 16:52:23
// Design Name:
// Module Name: ram_read_tb
// Project Name:
// Target Devices:
// Tool Versions: 2017.4
// Description:
// Dependencies:
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//
module ram_read_tb();
reg clk;
reg rst_n;
reg start;
reg [10 : 0] addr;
reg [31 : 0] din;
wire over;
wire [31 : 0] dout;
ram_read u1_ram_read(
.clk(clk),
.rst_n(rst_n),
.start(start),
.over(over),
.addr(addr),
.din(din),
.dout(dout)
);
always #5 clk=~clk;
initial begin
clk=1'b0;rst_n=1'b1;
#5; rst_n=1'b0;
#15; rst_n=1'b1;
start=1'b1;
addr=11'd0;
#30 start=1'b0;
end
endmodule
3. Simulation analysis
Part of the initial storage data is shown in Figure 5, and the simulation results are shown in Figure 6. It can be seen that the simulation results are correct, and the data at address 0 has been read successfully. Due to the output buffer, there will be a delay.
Summarize
This is the end of this introduction, a brief introduction to the use of the RAM IP core in vivado .