Vivado IP core's complex floating-point number accumulation Floating-point quickly realizes the addition of multiple data
Table of contents
foreword
In FPGA, the accumulation of floating-point numbers is often designed. The simple addition of two or two will take up a lot of clock cycles. It is very convenient to find that the Floating-point IP core provided by xilinx has an accumulation function. , can save a lot of clock cycles. The last time I searched the Internet for a long time, I didn't find the configuration of the accumulation IP core, so I plan to record the operation process of the accumulation of the IP core.
Tip: The following is the text of this article, all of which are original by the author himself. It is not easy to write an article. I hope you will attach a link to this article when reposting.
1. Floating-point IP core configuration steps
The picture above is an explanation of the configuration of those digits. The reason for configuring them is that this IP core does not directly accumulate floating-point numbers, but converts them to fixed-point numbers and then converts them back to floating-point numbers after the accumulation is completed. It is said in the picture that you can configure the number of digits it recommends to accumulate. Although there is a process of converting to fixed-point numbers, it is the same as using single-precision floating-point numbers to accumulate. That is, when the number of digits reaches a certain requirement, the accuracy can be completely guaranteed. Here I did not configure the number of bits so high, if the configuration is too high, it will require a lot of DSP resources.
2. Simulation
1. Top-level code
code show as below:
`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/09/15 19:55:41
// Design Name:
// Module Name: complex_accumulator_ip
// Project Name:
// Target Devices:
// Tool Versions: 2017.4
// Description:
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
module complex_accumulator_ip(
input clk ,
input valid ,//执行加法有效信号
input [ 31:0] re_a ,//复数a的实部
input [ 31:0] im_a ,//复数a的虚部
input last ,//累加最后一个数据标志信号
output res_valid ,//结果有效信号
output res_last ,//全部数据累加完标志信号
output [ 31:0] re_res ,//运算结果实部
output [ 31:0] im_res //运算结果虚部
);
float_accumulator_ip u1_float_accumulator_ip( //实部累加
.aclk (clk ),
.s_axis_a_tvalid (valid ),
.s_axis_a_tdata (re_a ),
.s_axis_a_tlast (last ),
.m_axis_result_tvalid (res_valid ),
.m_axis_result_tdata (re_res ),
.m_axis_result_tlast (res_last )
);
float_accumulator_ip u2_float_accumulator_ip( //虚部累加
.aclk (clk ),
.s_axis_a_tvalid (valid ),
.s_axis_a_tdata (im_a ),
.s_axis_a_tlast (last ),
.m_axis_result_tvalid ( ),
.m_axis_result_tdata (im_res ),
.m_axis_result_tlast ( )
);
endmodule
2. Simulation code
code show as below:
`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/09/15 19:56:43
// Design Name:
// Module Name: complex_accumulator_ip_tb
// Project Name:
// Target Devices:
// Tool Versions: 2017.4
// Description:
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
module complex_accumulator_ip_tb();
reg clk ;
reg valid ;
reg [ 31:0] re_a ;
reg [ 31:0] im_a ;
reg last ;
wire [ 31:0] re_res ;
wire [ 31:0] im_res ;
wire res_valid ;
wire res_last ;
always #1 clk=!clk;
initial begin clk=0;valid=0;last=0;re_a=0;im_a=0;
#1 last=0;
#2 re_a=32'b00111111100000000000000000000000; //1
im_a=32'b00111111100000000000000000000000; //1
valid=1;
#2 re_a=32'b01000000000000000000000000000000; //2
im_a=32'b01000000000000000000000000000000; //2
#2 re_a=32'b01000000010000000000000000000000; //3
im_a=32'b01000000010000000000000000000000; //3
last=1;
#2 last=0;valid=0;
//#3 valid=0;
end
complex_accumulator_ip u1_complex_accumulator_ip(
.clk (clk ),
.last (last ),
.valid (valid ),//执行加法有效信号
.re_a (re_a ),//复数a的实部
.im_a (im_a ),//复数a的虚部
.re_res (re_res ),//运算结果实部
.im_res (im_res ),//运算结果虚部
.res_valid (res_valid ),
.res_last (res_last )
);
endmodule
3. Simulation result analysis
The simulation results are shown in the figure. It can be seen that the module successfully realizes the accumulation of 3 complex floating-point numbers, and the output delay of the result is 26 clock cycles, which is consistent with the delay of the previous IP core configuration.
Summarize
The above is what I want to talk about today. This article only briefly introduces how to use the IP core to quickly realize the basic operation of complex floating-point number accumulation. If you want to use it to complete more data accumulation, you need to modify the code or understand the operation. Write code.