foreword

With the continuous development of the manufacturing process, the field programmable logic gate array (FPGA) is becoming more and more integrated, and its application is becoming more and more extensive. Among them, some mathematical processing IP must be used when processing digital signals. nuclear. Recently, I am studying the FPGA hardware implementation of airspace adaptive anti-interference technology research, which inevitably uses some IP cores. Today, I will introduce the Floating-point IP core in vivado in detail from the addition and subtraction of floating point numbers . I hope it will be helpful to everyone. Learning can help.

Tip: The following is the text of this article, all of which are original by the author himself. It is not easy to write an article. I hope you will attach a link to this article when reposting.

1. Example of addition and subtraction of floating point numbers

In order to facilitate the analysis of the results of the subsequent simulation, here we list the examples of floating-point addition and subtraction. During the simulation, directly use the following examples to simulate and verify whether the simulation results are correct.

example : Let the floating point number a=32'b1100_0000_1101_0011_0011_0011_0011_0011, that is, a=-6.6, the floating point number b=32'b0100_0001_0000_1100_1100_1100_1100_1100_1101, that is, b=8.8, then a +b=32'b0100_0000_0000_1100_1100_1100_1100_1110, that is, a+b=2.2000003 (the reason is not equal to 2.2, because the floating-point representation itself has a precision problem), ab=32'b1100_0001_0111_0110_0110_0110_0110_0110, that is, ab=-15.4.

2. Configuration instructions

Since a Floating-point IP core is called this time to achieve both addition and subtraction, there must be a control signal to control whether to perform addition or subtraction. This control signal is 6 bits in the data sheet, but it actually has 8 bits when generating the IP core, and the upper two bits are configured as 0 by default. The specific configuration is shown in Figure 1.

**Figure 1 Description of addition and subtraction configuration**

3. Floating-point IP core configuration steps

Search for Floating-point in vivado, and after finding the IP core, you can complete the corresponding configuration according to the following operations.

1. First configure the Operation Selection interface, as shown in Figure 2.

**Figure 2 Configuration of the Operation Selection interface**

2. Next, configure the Precision of Inputs interface, as shown in Figure 3.

**Figure 3** **Configuration of** the Precision of Inputs interface

3. Then configure the Optimizations interface, as shown in Figure 4.

**Figure 4** **Configuration of** the Optimizations interface

4. Finally, configure the Interface Options interface, as shown in Figure 5.

**Figure 5** Interface Options **interface configuration**

After the above 4 interfaces are configured, click the OK button in the lower right corner to generate the IP core.

4. Simulation

1. Top-level code

Create a top-level module named float_add_sub to instantiate the IP core just generated.

code show as below:

`timescale 1ns / 1ps
//
// Company: cq university
// Engineer: clg
// Create Date: 2022/07/23 12:19:25
// Design Name: 
// Module Name: float_add_sub
// Project Name: 
// Target Devices: 
// Tool Versions: 2017.4
// Description: 
// Dependencies: 
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//

module float_add_sub(
     input clk,
     input a_tvalid,
     input [31:0] a_tdata,
     input b_tvalid,
     input [31:0] b_tdata,
     input operation_tvalid,
     input [7:0] operation_tdata,
     output result_tvalid,
     output [31:0] result_tdata
    );
    
    float_add_sub_ip float_add_sub_ip_u1(
      .aclk(clk),
      .s_axis_a_tvalid(a_tvalid),
      .s_axis_a_tdata(a_tdata),
      .s_axis_b_tvalid(b_tvalid),
      .s_axis_b_tdata(b_tdata),
      .s_axis_operation_tvalid(operation_tvalid),
      .s_axis_operation_tdata(operation_tdata),
      .m_axis_result_tvalid(result_tvalid),
      .m_axis_result_tdata(result_tdata)
    );
    
endmodule

2. Simulation code

Create a simulation module named float_add_sub_tb , which is used to simulate the IP core instantiated by the top-level module just now.

code show as below:

`timescale 1ns / 1ps
//
// Company: cq uiniversity
// Engineer: clg
// Create Date: 2022/07/23 12:34:59
// Design Name: 
// Module Name: float_add_sub_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 2017.4
// Description: 
// Dependencies: 
// Revision:1.0
// Revision 0.01 - File Created
// Additional Comments:
//

module float_add_sub_tb();
     reg clk;
     reg a_tvalid;
     reg [31:0] a_tdata;
     reg b_tvalid;
     reg [31:0] b_tdata;
     reg operation_tvalid;
     reg [7:0] operation_tdata;
     wire result_tvalid;
     wire [31:0] result_tdata;

float_add_sub u1_float_add_sub(
      .clk(clk),
      .a_tvalid(a_tvalid),
      .a_tdata(a_tdata),
      .b_tvalid(b_tvalid),
      .b_tdata(b_tdata),
      .operation_tvalid(operation_tvalid),
      .operation_tdata(operation_tdata),
      .result_tvalid(result_tvalid),
      .result_tdata(result_tdata)
);
always #5 clk=~clk;
   
initial begin
    clk=1'b0;
#10;     a_tvalid<=1'b1;
            a_tdata<=32'b1100_0000_1101_0011_0011_0011_0011_0011;
            b_tvalid<=1'b1;
            b_tdata<=32'b0100_0001_0000_1100_1100_1100_1100_1101;    
            operation_tvalid<=1'b1;
            operation_tdata<=8'b0000_0000;        //加法
 #400;  a_tvalid<=1'b1;
            b_tvalid<=1'b1;
            operation_tvalid<=1'b1;
            operation_tdata<=8'b0000_0001;        //减法
end

always @(posedge clk) begin
        if (result_tvalid == 1'b1)  begin
            a_tvalid <=1'b0;
            b_tvalid<=1'b0;
           operation_tvalid <= 1'b0;
        end      
    end

endmodule

5. Simulation Analysis

The simulation results are shown in Figure 6. Compared with the examples of floating-point addition and subtraction listed above, it can be seen that the module has successfully implemented the addition and subtraction of floating-point numbers.

Summarize

This time I introduced how to use the Floating-point IP core in vivado to implement the addition and subtraction of floating-point numbers.

Vivado IP core floating-point addition and subtraction Floating-point