Verilog is used very little, here is a brief introduction to MyHDL.
The purpose of this tool is to write verilog code in Python. Of course, you must first install Python, and then install its extension MYHDL (pip install myhdl), and a tool called gtkWave is also necessary.
There are many examples on the official website, just choose one to introduce, the address is:
http://www.myhdl.org/docs/examples/flipflops.html
Do a simple and quick introduction, the others are similar operations, source code (file name is flip-flop_tb.py)
from myhdl import *
from random import randrange
def dff(q, d, clk):
@always(clk.posedge)
def logic():
q.next = d
return logic
def test_dff():
q, d, clk = [Signal(bool(0)) for i in range(3)]
dff_inst = dff(q, d, clk)
@always(delay(10))
def clkgen():
clk.next = not clk
@always(clk.negedge)
def stimulus():
d.next = randrange(2)
return dff_inst, clkgen, stimulus
def simulate(timesteps):
tb = traceSignals(test_dff)
sim = Simulation(tb)
sim.run(timesteps)
def convert():
q, d, clk = [Signal(bool(0)) for i in range(3)]
toVerilog(dff, q, d, clk)
simulate(2000)
convert()To put it simply, simulate is to do a simulation to see if the waveform is correct, and a waveform file named
test_dff.vcd will be generated in the directory when running
.
Viewing the waveform is very simple. Whether you use the command mode or the graphical interface, the result is the same. The command mode I used:
gtkwave test_dff.vcd，
At this time, the waveform will be opened, and after zooming out and adjusting, you can see the following results,
Convert is to convert the definition of dff into verilog code. After running, it will generate a file called dff.v, its content is as follows
// File: dff.v
// Generated by MyHDL 0.11
// Date: Tue Oct 13 14:52:37 2020
`timescale 1ns/10ps
module dff (
q,
d,
clk
);
output q;
reg q;
input d;
input clk;
always @(posedge clk) begin: DFF_LOGIC
q <= d;
end
endmodule