First of all
![](https://upload-images.jianshu.io/upload_images/16981913-940a46076288c199.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
Then populated write their own code
After the save as to save their own folders
It will automatically pop up
![](https://upload-images.jianshu.io/upload_images/16981913-8f419c51571b0996.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
Configuration
![](https://upload-images.jianshu.io/upload_images/16981913-1fc7bd5bf58a69f6.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
![](https://upload-images.jianshu.io/upload_images/16981913-85fd877289eec04e.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
Assignments settings
![](https://upload-images.jianshu.io/upload_images/16981913-ab7bfa1056a2d87f.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
After the first compilation
成功后processing start start testbench template writer
After going under the saved file, here is a simulation folder, find XXX.vt file, open, save as XX_test_tb.v. (Note saveas to the top-level folder) modify the contents of design documents for their own good test
After compiling again qutartus
After successful tools netlist viewer rtlviewer can see rtl netlist map.
![](https://upload-images.jianshu.io/upload_images/16981913-8b1ffd6510c6bc64.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
After the tools runsimulationtools rtl level simulation
pop up
![](https://upload-images.jianshu.io/upload_images/16981913-b6845f160e73c3a3.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
Tools options general edatooloptions
Add modelsim altera path
Here is the general quartus and bound together, found himself a bit, better looking.
![](https://upload-images.jianshu.io/upload_images/16981913-d9ccfa0979e2ebb9.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
After the tools runsimulationtools rtl level simulation
Then there is a problem, can not find test_tb
Back to qutartus.
Assignments settings
![](https://upload-images.jianshu.io/upload_images/16981913-880a29d3b7236f61.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
Test benches new
File name just add top-level file test_tb
Note Do not forget to fill in testbenchname
![](https://upload-images.jianshu.io/upload_images/16981913-89cc34562731d05b.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
![](https://upload-images.jianshu.io/upload_images/16981913-fb376c0ab3958733.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)
After recompiling
After the tools runsimulationtools rtl level simulation
Simulate start simulation work选择test_tb
Add wave, see (Note that this unit is ps, so you may want to run a long time to change, to be flexible and use the magnifying glass)
![](https://upload-images.jianshu.io/upload_images/16981913-fb759fac4ca6565c.png?imageMogr2/auto-orient/strip%7CimageView2/2/w/1240)