1. Basic knowledge
1. PCI-Express is a high-speed serial computer expansion bus standard, which was proposed by Intel in 2001 to replace the old PCI, PCI-X and AGP bus standards.
Like most buses, the PCIe bus also includes electrical properties and protocol components .
The PCIe specification adopts a layered structure for device design, which consists of a transmission layer, a data link layer, and a physical layer. Each layer is divided into two functional blocks: sending and receiving.
At the sending end, the application (device core A) forms a transaction layer package (TLP-Transaction Layer Package) at the transport layer, stores it in the sending buffer, and waits to be pushed to the lower layer.
The data link layer, and then concatenated packet TLP on additional information that is received when the other error checking TLP packet to use to form a data link layer packet (DLLP - Data Link Layer Package) ;
in The physical layer encodes the DLLP packet, occupies the available channel in the link, and sends it out from the transmitter.
At the receiving end, it is actually the "reverse" process at the sending end. If the sending end is constantly grouping packages, then the receiving end is constantly unpacking, and finally extracts useful data information for use by the application of the B device.
The whole process is actually very similar to the process of Ethernet, in which data is expanded at different levels. In the FPGA development process, in fact, from the transaction layer to the physical layer are encapsulated, forming a standard IP core . The user exchanges data with the bus protocol (such as AXI4-Stream) required by the IP core.
2. Data transmission method
PCIe bus specifies two types of data transmission methods, namely Non-Posted and Posted data transmission methods.
For non-posted bus transactions, the "one question, one answer" approach is that the sender first submits a bus read and write request to the receiver, and then the receiver sends a completion (Completion) message to the sender.
The PCIe bus uses the Split transfer method to process all Non-Posted bus transactions, such as memory read, I/O read and write, and configuration read and write.
In the posted bus transaction, the "one-way sending" mode only sends messages to the terminal, and the terminal does not need to feed back the completed message.
3. PCIe is compatible with PCI at the software level, that is to say, the PCIe bus can be configured using the PCI access method. PCIe devices generally have BusNO/DeviceNO/Function. Usually DeviceNO is 0.
In addition, a memory mapping method is provided to access PCIe devices—PCIe enhance configuration mechanism. A total of 256Mbyte of space will be occupied.
2. Configuration read and write
1. The PCI bus specifies three types of PCI configuration space, which are: the configuration space used by the
PCI Agent device , and the configuration space used by the
PCI bridge . The configuration space used by the
Cardbus bridge .
It is worth noting that the addresses appearing in the PCI device configuration space are all PCI bus addresses, which belong to the PCI bus domain address space.
3. Data read and write (assuming that the configuration space has been initialized by the system software)
PCI bus supports the following types of memory read and write bus transactions.
1. The HOST processor reads and writes data in the BAR space of the PCI device . The BAR space can use memory or I/O decoding methods. The HOST processor uses the PCI bus's memory read and write bus transactions and I/O read and write bus transactions to access the BAR (base address, that is, data base address) space of the PCI device.
2. Data transfer between PCI devices. Two devices on the PCI bus can communicate directly. For example, one PCI device can access the BAR space of another device. However, this kind of data transfer is rarely used in PC processor systems.
3. The PCI device reads and writes the main memory , that is, DMA read and write operations .
DMA read and write operations are commonly used in all processor systems, and are also the focus of PCI bus data transfer.
In most cases, the end of the DMA read and write operation will be accompanied by an interrupt. PCI devices can use INTA#, INTB#, INTC#, and INTD# signals to submit interrupt requests, or use MSI mechanisms to submit interrupt requests.
(When the PCI device transfers data to the main memory through DMA, the data in the memory may not be immediately available when an interrupt request is received, and it needs to be read first)
(1)Posted process: PCI device 11 performs DMA write operation to the memory as an example
1>When PCI device 11 obtains the right to use PCI bus x1, it will send the memory write bus transaction to PCI bus x1
2>When PCI bridge 1 finds that the address of this bus transaction is not within the address range it manages, it will first receive this bus transaction and end the PCI bus x1 bus transaction
3> After PCI bridge 1 obtains the right to use PCI bus x0, it will forward the memory write bus transaction to PCI bus x0
4>After that, the host host bridge x will receive the memory write bus transaction , and finally write the data into the memory. Release bus resources step by step!
(2) PCI device 11 performs DMA write operation:
1>The PCI device sends the memory write request of the processor to the PCI bus x1.
2>All devices on the PCI bus monitor this request. Since it is a memory write request to the processor , the PCI agent on the PCI bus will not receive this request.
3>PCI bridge x1 finds that the PCI bus address used by the current bus transaction is not the PCI domain address of its downstream device, so it receives this request. At this time, PCI bridge x1 ends the posted memory write request from PCI device 11 and pushes this request to On PCI bus 0.
4>All PCI devices including the host bridge monitor this request. HOST host bridge x ends the posted memory write request of PCI bridge x1 .
5> The HOST host bridge x finds that this data request is sent to the memory, converts the PCI domain address into a memory address , and then writes the data into the memory through the memory controller.