Overview
This article is mainly a summary of some issues about PCIe. This article is written wherever I think of it. The order may not be very friendly. I have not been exposed to PCIe for a long time, and there are many things that are not clear. , I am still continuing to learn, and I hope to make progress together with everyone. Please forgive me for any shortcomings. If you have any questions, please leave a message in the comments to discuss together.
This article will also continue to add questions.
Problem summary
1.Is Bar0 necessarily the first Bar used?
Through previous studies, we know that the enumeration driver's operations on BAR must be performed sequentially, that is, first BAR0, then BAR1,..., until BAR5. When the software detects BARs that are set to all 0s by the hardware, it assumes that the BAR is not in use. Whether it is PCI or PCIe, there is no clear stipulation that the first BAR used must be BAR0. In fact, as long as the designer has the original intention, BAR4 can be used as the first BAR, and BAR0~BAR3 can be set to not be used.
2. Which PCIe devices are multi-function devices?
Each PCIe device has up to 8 Functions. When the number of Functions is greater than 1, it is called a multi-function device. PCIe devices with multi-functions are not universal features of all devices. Most PCIe devices are single-function devices. Functional devices;
Common multifunctional devices include:
- Network adapter: Some high-performance network adapters can provide multiple virtual network interface functions, each function can run independently to achieve multiple network connections.
- RAID Controller: Some RAID controllers can have multiple independent functions, each of which can control an independent RAID array. This means that a single RAID controller can manage multiple independent hard drive arrays.
- Graphics Card: Some high-performance graphics cards may have multiple display output capabilities. Each function can drive an independent display, enabling multi-monitor configurations.
- Multiport serial cards: Some serial interface cards can have multiple independent serial port functions. Each function can communicate with different devices.
4. How to know the training status of the current equipment
How to know the Link rate and line num of the current device
You can read the PCI Express Capability Structure, the PCI capability ID is 0x10, and query the manual to know the current rate and line num. line.
5. About the relationship between PCI domain address and memory domain address
The processor system shown in the picture above consists of a CPU, a DRAM controller and two HOST main bridges. In this processor system, it includes the CPU domain, DRAM domain, memory domain and PCI bus domain address space. Among them, HOST main bridge x and HOST main bridge y manage PCI bus x domain and PCI bus y domain respectively. When a PCI device accesses the memory domain, it also needs to go through the HOST main bridge, and the HOST main bridge performs address translation from the PCI bus domain to the memory domain; when the CPU accesses the PCI device, it also needs to go through the HOST main bridge to perform address translation from the memory domain to the PCI bus domain. Address translation.
In a processor system, the PCI bus addresses that the CPU can access must have address mappings in the memory domain; and the addresses of the memory domains that PCI devices can access must also have address mappings in the PCI bus domain. Some processors provide registers for this address mapping, such as PowerPC's inbound and outbound register groups (PowerPC's RapidIO bus domain address mapping is also managed through inbound and outbound register groups). Some processors do not provide similar registers, but the conversion between the memory domain and the PCI bus domain always exists.
This article will continue to be updated in the future, and additions are welcome.