zynq AXI is very important content, this article is only a brief introduction. Lots of references to other books.
AXI ( Advanced eXtensible Interface ) is a bus protocol proposed by ARM , Xilinx
The AXI bus is supported from the 6 series FPGA , and the AXI4 version is currently used.
1. AXI bus
ZYNQ has three AXI buses:
( 1 ) AXI4 : ( For high-performance memory-mapped requirements. ) It is mainly oriented to the requirements of high-performance address mapping communication, and is an address mapping-oriented interface, allowing a maximum of 256 rounds of data burst transmission;
( 2 ) AXI4-Lite : ( For simple, low-throughput memory-mapped communication ) is a lightweight address-mapped single-transfer interface that occupies very few logical units.
( 3 ) AXI4-Stream : ( For high-speed streaming data. ) For high-speed streaming data transmission; the address item is removed, allowing unlimited data burst transmission scale.
The AXI4 bus and the AXI4-Lite bus have the same components:
( 1 ) Read address channel, including ARVALID, ARADDR, ARREADY signals;
( 2 ) Read data channel, including RVALID, RDATA, RREADY, RRESP signals;
( 3 ) Write address channel, including AWVALID , AWADDR, AWREADY signals;
( 4 ) Write data channel, including WVALID, WDATA , WSTRB, WREADY signals;
( 5 ) Write response channel, including BVALID, BRESP, BREADY signals;
( 6 ) System channel, including: ACLK , ARESETN signal.
The AXI4-Stream bus consists of:
( 1 ) ACLK signal: bus clock, valid on rising edge;
( 2 ) ARESETN signal: bus reset, active low
( 3 ) TREADY signal: the slave tells the master to prepare for transmission;
( 4 ) TDATA signal: data, optional width 32, 64, 128 , 256bit
( 5 ) TSTRB signal: each bit corresponds to a valid byte of TDATA, the width is TDATA /8
( 6 ) TLAST signal: the master tells the slave that this transfer is the end of the burst transfer;
( 7 ) TVALID signal: the host tells the slave that the data is valid this time;
( 8 ) TUSER signal: user-defined signal, the width is 128bit .
2. AXI interface
AXI has three interfaces:
( 1 ) AXI-GP interface ( 4 ): It is a general AXI interface, including two 32 -bit master device interfaces and two 32 -bit slave device interfaces, which can be used to access the on-chip peripherals in the PS .
( 2 ) AXI-HP interface ( 4 ): It is a standard interface of high performance / bandwidth, and the PL module is connected as the main device (as can be seen from the arrow in the figure below). Mainly used by PL to access memory on PS ( DDR and On-Chip RAM )
( 3 ) AXI-ACP interface ( 1 ): It is an interface defined under the ARM multi-core architecture. It is translated into accelerator coherence port in Chinese. It is used to manage AXI peripherals without cache such as DMA . The PS side is Slave interface.
3. AXI protocol
The formulation of the protocol is based on the bus composition. So say AXI4 , AXI4-Lite , AXI4-Stream are all AXI4 protocol. The two ends of the AXI bus protocol can be divided into master ( master ) and slave ( slave ) ends, which generally need to be connected through an AXI Interconnect , which is used to provide one or more AXI master devices to connect to one or more A switching mechanism for multiple AXI slave devices.
The main role of AXI Interconnect is that when there are multiple masters and slaves, AXIInterconnect is responsible for linking and managing them. Since AXI supports out-of-order transmission, out-of-order transmission requires the support of the ID signal of the host, and the ID sent by different hosts may be the same, and AXI Interconnect solves this problem. It will process the ID signals of different hosts to make the ID become only.
The AXI protocol separates the read address channel, read data channel, write address channel, write data channel, and write response channel, and each channel has its own handshake protocol. Each channel does not interfere with each other but depends on each other. This is one of the reasons why AXI is so efficient.
3.1AXI handshake protocol
What AXI4 uses is a READY , VALID handshake communication mechanism. Simply put, there is a handshake process before the master and slave parties communicate data. The transmission source generates the VLAID signal to indicate when data or control information is valid.
The destination source generates a READY signal to indicate that it is ready to receive data or control information. A transfer occurs when both the VALID and READY signals are high at the same time. An example in the following figure:
3.2 Burst read and write
( 1 ) Timing of burst read
After the address appears on the address bus, the transferred data will appear on the read data channel. The device keeps VALID low until the read data is valid. To indicate the completion of a burst read or write, the device uses the RLAST signal to indicate the last data transferred.
( 2 ) Timing of burst write
At the beginning of this process, the host sends address and control information to the write address channel, and then the host sends each write data to the write data channel. When the host sends the last data, the WLAST signal goes high. When the device has received all the data it sends a write response back to the host to indicate that the write transaction is complete.