Achieve the AXI DMA bus

In zynq series, PS and PL data exchange primarily through AXI bus for transmitting small amounts of data (e.g., configuration registers, status information acquisition, etc.) often adopt AXI4-LITE. For large, high-speed data transmission, often used AXI4-FULL. Although the official has a corresponding DMA module, but the principle of "self-sufficiency", combined with "for their own is the best," and make their own decisions based on AXI DMA controller.

Design goals:

PL hanging end PHY chip, the data exchange is completed and the PS network port PL terminal end, Note: PL and PS will automatically transmit data to the network port.

designing process:

Since PL and PS terminal automatically sends data to the network port, therefore, the PHY is mounted directly at the end of PS desirable, to do a separation of the multiplexed data network port.

After receiving an IP packet envisaged, FPGA, will automatically send data to the CPU, after the transmission is complete, FPGA generates an interrupt, then the CPU for processing, if it returns a result, the read data is sent to the network port automatically by the FPGA.

There are many custom IP design methodology online, not here in the repeat.

Here are summarized under the main design method AXI4 interface protocol. AXI4 protocol interface There are two main ways: First, the template is generated by the Vivado custom peripherals, AXI4 need to have a basic understanding. The second is produced by HLS, we need to have some understanding of the HLS interface.

Compared to directly modify the template AXI4, personally recommend HLS interface design, compared to HLS AXI4 templates, you can avoid a lot of timing modification.

Generally, the length of the IP packet does not exceed 2K, therefore, a need in the FPGA end 2K memory. 11-bit length field.

Reference code as the receiving end:

void phy_rec_dma(ap_uint<8> in[2048],ap_uint<11> *in_len,ap_uint<8> out[2048],ap_uint<11> *out_len)
{
	*out_len = *in_len;
	for(int i=0;i<*in_len;i++){
		out[i] = in[i];
	}
}

Subsequently, in [2048] constrained FIFO or RAM, constrained to the m-axi out and set burst length, constrained to the out_len s-axilite, the default IO constrained to s-axilite. After a comprehensive implementation can be exported via IP.

Achieve the AXI DMA bus

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