1. Software setting interface
FIFO (First In First Out) is a data buffer used to read and write data first in first out. Different from the address-based reading and writing method of ROM or RAM, the reading and writing of FIFO follows the principle of "first in, first out", that is, data is written into FIFO in order, and the data written first is also read out first when reading. So FIFO memory has no address lines. The FIFO has a write port and a read port, and the user does not need to control the address externally, so it is easy to use.
The FIFO memory is mainly used as a cache. It is used in synchronous clock systems and asynchronous clock systems. It is used in many designs, such as: multi-bit data for cross-clock domain conversion, front and rear bandwidth asynchronous, etc. Asynchronous FIFO is used, schematic diagram as follows. FIFO is divided into SCFIFO (synchronous FIFO) and DCFIFO (asynchronous FIFO) according to whether the read and write clocks are the same. SCFIFO reads and writes with the same clock and is applied in a synchronous clock system; DCFIFO has different read and write clocks and is applied in an asynchronous clock system .
There are no special things to pay attention to when using the FIFO of Yilinx fpga. It is also a visual interface. According to the definition of the interface, it can be set normally to generate FIFO.
The steps of FIFO generation are described in detail below.
Open any project, in the IPM menu bar, double-click FIFO IP;
To generate IP, you need to name it at the module name, and
enable some indication signals in the configuration interface as needed;
Click generate in the lower right corner to generate.
two.
FIFO port definition
three.
FIFO timing
Synchronous FIFO standard mode
Synchronous FIFO FWFT mode
Asynchronous FIFO standard mode
Asynchronous FIFO FWFT mode
For more details about the application of Yilinx FPGA, please refer to the link below:
New Product Launch--EFINIX FPGA Programmer
Yilinsi FPGA --- localization alternative selection strategy
Collection of PLL usage of domestic Yilinsi FPGA
Domestic FPGA Application Topic--Experience in Using Efinity Software
good news! The purely localized Yilinsi T20 core board is on sale!