[FPGA IP Series] Detailed explanation of FIFO depth calculation

FIFO (First In First Out) is a first-in, first-out storage structure that is often used to cache data or match transmission rates in FPGA designs.

A key parameter of FIFO is its depth, which is the number of data items that FIFO can store. Reasonable depth design can prevent data overflow and save FPGA resource consumption.

1. Factors affecting FIFO depth calculation

The main factors affecting FIFO depth calculation include:

• FIFO bit width: determines the size of each FIFO storage unit

• FIFO data word length: determines how many bits of valid data each data word contains

• The total storage capacity of FIFO: determines the maximum number of data items that can be stored

Taking a FIFO with a width of 32 bits and a word length of 8 bits as an example, each FIFO storage unit requires 32/8=4 bytes.

If the total capacity of FIFO is 128 bytes, then 128/4=32 data can be stored.

In addition, FIFO depth also needs to be considered:

• FPGA resource constraints: Too large a FIFO will occupy too many resources

• Practical application requirements: Too small a depth may result in data loss

• Storage density: Choosing an integer power of 2 as the depth can optimize resource utilization

Determine the optimal FIFO depth after comprehensively considering the above factors.

2. FIFO depth calculation steps

The basic steps for FPGA FIFO depth calculation are as follows:

• According to the worst case of transmission (when the amount of cached data is the largest within a period of time), the remaining data amount (amount of written data - amount of read data) is calculated.

• Calculate the maximum amount of data that the FIFO can store based on the total remaining data storage capacity/write bit width

• Select a power of 2 greater than or equal to the maximum data amount as the FIFO depth

• Convert FIFO depth to binary representation

If writing is slower than reading, then there is no need to worry about data overflow. Only when reading is slower than writing, fifo depth design needs to be considered to prevent data overflow.

3. Verilog code example

Here is an example of calculating FIFO depth using Verilog code:

// FIFO参数  
parameter DATA_WIDTH = 32; // 32位
parameter WORD_SIZE = 8;  // 8位字长 
parameter FIFO_SIZE = 128; // 总容量128字节

// 每个FIFO存储单元的大小
localparam FIFO_CELL_SIZE = DATA_WIDTH / WORD_SIZE;

// FIFO最大可存储数据量
localparam FIFO_MAX_WORDS = FIFO_SIZE / FIFO_CELL_SIZE;  

// 选择大于FIFO_MAX_WORDS的2的幂  
localparam FIFO_DEPTH = (FIFO_MAX_WORDS > 0) ?  
                       (2**$clog2(FIFO_MAX_WORDS)) : 1;
                       
// FIFO深度比特宽
localparam FIFO_DEPTH_WIDTH = $clog2(FIFO_DEPTH);

In this example, based on the bit width of 32 bits, word length of 8 bits and capacity of 128 bytes, the FIFO depth is calculated to be 32, which requires 5 bits to represent.

4. SystemVerilog code example

Here is the equivalent code written in SystemVerilog:

// FIFO参数
localparam int DATA_WIDTH = 32; 
localparam int WORD_SIZE = 8;
localparam int FIFO_SIZE = 128;

// 每个FIFO存储单元的大小  
localparam int FIFO_CELL_SIZE = DATA_WIDTH / WORD_SIZE;

// FIFO最大可存储数据量
localparam int FIFO_MAX_WORDS = FIFO_SIZE / FIFO_CELL_SIZE;

// 选择大于FIFO_MAX_WORDS的2的幂 
localparam int FIFO_DEPTH = (FIFO_MAX_WORDS > 0) ? 
                            2**(FIFO_MAX_WORDS.log2) : 1;
                            
// FIFO深度比特宽            
localparam int FIFO_DEPTH_WIDTH = $clog2(FIFO_DEPTH);

SystemVerilog simplifies code by using the built-in log2 function.

5. FIFO depth calculation example

The FIFO depth calculation process is further explained below through some specific examples.

1. Match data bandwidth

If the FIFO needs to match the specified data bandwidth, then the depth calculation must take into account the impact of the serialization factor.

For example, if a 200MHz serial LVDS interface is required and 10-bit data is used, 200MHz * 10 bits = 2Gbps data can be transmitted per unit time.

If the backend interface is 32 bits wide and 100MHz, then its bandwidth is 100MHz * 32 bits = 3.2Gbps. In order to match the bandwidth, the front-end data needs to be cached. At this time, the FIFO depth is calculated as follows:

后端带宽 = 3.2Gbps  
前端带宽 = 2Gbps
串行化因子 = 后端带宽/前端带宽 = 3.2/2 = 1.6  
FIFO深度 > 串行化因子 = 1.6

Therefore, choose a FIFO depth of 2 to match the bandwidth requirements.

2. Prevent data overflow

If the data rate written to the FIFO may be higher than the read rate, then the FIFO depth needs to be increased to prevent data overflow.

Scenario 1: If the write rate is 100MB/s, the read rate is 80MB/s, and the maximum allowed waiting time is 50μs, then the required FIFO size is calculated as follows:

写入速率 = 100MB/s
读取速率 = 80MB/s 
最大等待时间 = 50μs
额外存储量 = 写入速率 × 最大等待时间  
          = 100MB/s × 50μs
          = 5000bit

Therefore, the FIFO depth needs to consider the additional storage of 5000 bits of data, that is, in addition to the normal storage amount, it is also necessary to ensure that there is at least 5000 bits of additional FIFO depth.

Scenario 2: Asynchronous FIFO, write clock 100MHZ, read clock 80MHZ. The read and write bit widths are both 16 bits. It is known that up to 960 bits of data can be written every 100 write cycles, and the read side reads one data per clock. Q: What is the minimum FIFO depth?

最恶劣情况：前100个周期的后连续60个周期写入960bit数据，后100个周期的前连续60个周期写入960bit数据。

写数据：最大数量为连续120个写周期内，写入数据量960*2bit = 1920 bit，用时为120/100 ns。

读数据：这段时间内的数据量为 120/100 * 80 * 16bit = 1536 bit 。

最大缓存数据量为 1920 - 1536 = 384 bit

写数据最大缓存深度：384/16 = 24

最大深度需要是2的幂次方，即为32

3. Optimize resource utilization

Sometimes in order to optimize resource utilization, it may be necessary to reduce the FIFO depth.

For example, according to bandwidth calculation, an 18Kb block RAM can achieve a FIFO of depth=512, but considering resource limitations, only a 9Kb RAM can be used. In this case, the FIFO can be designed as depth=256 to save block RAM resources.

Similarly, in order to optimize resource utilization, the FIFO depth is usually designed to be an integer power of 2, which can reduce the resources required for address decoding logic.

6. Conclusion

FIFO depth calculation is not complicated, but many practical factors need to be considered, such as bandwidth matching, overflow prevention, and resource optimization. Generally speaking, the maximum depth is calculated based on the storage requirements, and then resource and performance constraints are comprehensively considered, and a power of 2 greater than or equal to the maximum depth is selected as the final FIFO depth, which can not only meet the storage requirements, but also optimize FPGA resource utilization.

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