0 Overview
RV32C is an instruction set in the RISC-V architecture, and its design goal is to provide efficient instruction compression technology while maintaining the simplicity and flexibility of the RISC-V architecture. It is an important extension in the RISC-V architecture, which provides convenience and support for embedded systems and low-power devices. RISC-V architecture based on 32-bit registers, while adding a compressed instruction set (C), which can compress 32-bit instructions into 16-bit or shorter instructions, thereby reducing the overhead of instruction storage and transmission, and improving the cache efficiency of instructions. Reduce power consumption and cost at the same time.
The RV32C instruction set contains some commonly used instructions, such as arithmetic, logic, data transfer, branch and jump instructions. Although these instructions can be compressed into 16-bit or shorter instructions, they function the same as 32-bit instructions. In addition, some special compression registers are provided for storing the results of compressed instructions.
In general, RV32C is an extension of the RISC-V architecture. It provides programmers with a compressed form of some commonly used instructions, which can reduce the overhead of instruction storage and transmission, improve the cache efficiency of instructions, and also reduce power consumption. Consumption and cost.
1 Overview of RV32C instruction set
Compared with ARM and MIPS, which designed the instruction set from the heart in order to reduce the code, RV32C adopts a novel method: each short instruction must correspond to a standard 32-bit RISC-V instruction one-to-one. In addition, 16-bit instructions are only visible to the assembler and linker. Whether to replace the corresponding wide instructions with short instructions is their own decision, which is very happy for compiler writers and assembly language programs. Based on observation of the program it was found that:
- The frequency of access to ten commonly used registers (a0-a5, s0-s1, sp and ra) is far higher than that of other registers;
- The write destination of many instructions is one of their source operands;
- Immediate numbers tend to be small.
The instruction set of RV32C can be expressed as:
2 Detailed explanation of RV32C instruction set
2.1 Load/store instructions
2.1.1 C.LWSP instruction (c.lwsp rd,uimm(x2))
x[rd] = sext(M[x[2] + uimm][31:0])- Stack pointer related word loading (Load Word, Stack-Pointer Relative), the extended form is lw rd, uimm(x2), and it is illegal when rd=x0.
2.1.2 C.SWSP instruction (c.swsp rs2,uimm(x2))
M[x[2] + uimm][31:0] = x[rs2]- Stack pointer relative word storage (Store Word, Stack-Pointer Relative), the extended form is sw rs2, uimm(x2).
2.1.3 C.LW instruction (c.lw rd'',uimm(rs1'))
x[8+rd’] = sext(M[x[8+rs1’] + uimm][31:0])- Load Word, the extended form is lw rd,uimm(rs1), where rd=8+rd',rs1=8+rs1'
2.1.4 C.SW instruction (c.sw rs2', uimm(rs1'))
M[x[8+rs1’] + uimm][31:0] = x[8+rs2’]- Word storage (Store Word), the extended form is sw rs2,uimm(rs1), where rs2=8+rs2', rs1=8+rs1'.
2.2 Jump instructions
2.2.1 CJ instruction (cj offset)
pc += sext(offset)- Jump (Jump), the extended form is jal x0, offset
2.2.2 C.JAL instruction (c.jal offset)
x[1] = pc+2; pc += sext(offset)- Link jump (Jump and Link), the extended form is jal x1, offset
2.2.3 C.JALR instruction (c.jalr rs1)
t = pc+2; pc = x[rs1]; x[1] = t- Register link jump (Jump and Link Register), the extended form is jalr x1,0(rs1), and it is illegal when rs1=x0.
2.3 Judging branch instructions
2.3.1 C.BEQZ instruction (c.beqz rs1', offset)
if (x[8+rs1’] == 0) pc += sext(offset)- Equal to branch at zero time (Branch if Equal to Zero), the extended form is beq rs1,x0,offset, where rs1=8+rs1'.
2.3.2 C.BNEZ instruction (c.bnez rs1', offset)
if (x[8+rs1’] ≠ 0) pc += sext(offset)- Branch if Not Equal to Zero (Branch if Not Equal to Zero), the extended form is bne rs1,x0,ofset, where rs1=8+rs1'.
2.4 Arithmetic instructions
2.4.1 C.LI instruction (c.li rd, imm)
x[rd] = sext(imm)- Immediate load (Load Immediate), the extended form is addi rd, x0, imm.
2.4.2 C.LUI order（c.lui rd,imm）
x[rd] = sext(imm[17:12] << 12)- Load Upper Immediate (Load Upper Immediate), the extended form is lui rd, imm, when rd=x2 or imm=0 is illegal
2.4.3 C.ADDI instruction (c.addi rd,imm)
x[rd] = x[rd] + sext(imm)- Add immediate value (Add Immediate), the extended form is addi rd, rd, imm
2.4.4 C.ADDI16SP instruction (c.addi16sp imm)
x[2] = x[2] + sext(imm)- Add 16 times the immediate value to the stack pointer (Add Immediate, Scaled by 16, to Stack Pointer), the expansion form is addi x2, x2, imm, and imm=0 is illegal.
2.4.5 C.ADDI4SPN instruction (c.addi4spn rd', uimm)
x[8+rd’] = x[2] + uimm- Add 4 times the immediate value to the stack pointer (Add Immediate, Scaled by 4, to Stack Pointer, Nondestructive), the extended form is addi rd, x2, uimm, where rd=8+rd'. It is illegal when uimm=0.
2.4.6 C.SLLI instruction (c.slli rd, uimm)
x[rd] = x[rd] << uimm- Immediate logical left shift (Shift Left Logical Immediate), the extended form is slli rd, rd, uimm.
2.4.7 C.SRLI instruction (c.srli rd', uimm)
x[8+rd’] = x[8+rd’] >>u uimm- Immediate logical right shift (Shift Right Logical Immediate), the extended form is srli rd, rd, uimm, where rd=8+rd'.
2.4.8 C. SRAI instruction (srai rd', uimm)
x[8+rd’] = x[8+rd’] >>s uimm- Shift Right Arithmetic Immediate (Shift Right Arithmetic Immediate), the extended form is srai rd, rd, uimm, where rd=8+rd'.
2.4.9 C.ANDI instruction (c.andi rd', imm)
x[8+rd’] = x[8+rd’] & sext(imm)- And immediate (AND Immediate), the extended form is andi rd, rd, imm, where rd=8+rd'.
2.4.10 C.MV instruction (c.mv rd, rs2)
x[rd] = x[rs2]- Move (Move), the extension form is add, rd, x0, rs2, and it is illegal when rs2=0.
2.4.11 C.ADD instruction (c.add rd, rs2)
x[rd] = x[rd] + x[rs2]- Add (Add), the extended form is add rd, rd, rs2. Illegal when rd=x0 or rs2=x0.
2.4.12 C.AND instruction (c.and rd'.rs2')
x[8+rd’] = x[8+rd’] & x[8+rs2’]- And (AND), the extended form is and rd,rd,rs2, where rd=8+rd', rs2=8+rs2'.
2.4.13 C.OR instruction (c.or rd',rs2')
x[8+rd’] = x[8+rd’] | x[8+rs2’]- Or (OR), the extended form is or rd,rd,rs2, where rd=8+rd', rs2=8+rs2'.
2.4.14 C.XOR instruction (c.xor rd',rs2')
x[8+rd’] = x[8+rd’] ^ x[8+rs2’]- XOR (Exclusive-OR), the extended form is xor rd, rd, rs2, where rd=8+rd', rs2=8+rs2'.
2.4.15 C.SUB command (c.sub rd', rs2')
x[8+rd’] = x[8+rd’] - x[8+rs2’]- The extended form is sub rd,rd,rs2, where rd=8+rd', rs2=8+rs2'.
2.5 System commands
2.5.1 C.EBREAK instruction (c.ebreak)
RaiseException(Breakpoint)- Environment Breakpoint (Environment Breakpoint), the extended form is ebreak.
