July, RISC-V Foundation announced the approval of RISC-V basic instruction set architecture and privileged architecture specification , further laid the foundation for scalability of RISC-V. And recently, there are developers on this basis to open an F # implementation RISC-V officially ISA (Instruction Set Architecture) specification (to achieve).
RISC-V basic instruction set architecture is between the application software and hardware interfaces, coding standard software for this purpose will continue to permanent use on RISC-V processor, even through the development of a new extension architecture and development will not be affected.
Officials said RISC-V uses a simple fixed base and modular fixed standard ISA expansion designed to help prevent fragmentation, while supporting custom, eco-RISC-V has been demonstrated to a large extent on the various implementations of previous interoperability sex, and now ratified the infrastructure specifications, developers can further be assured that they are written for RISC-V software will be running on all similar RISC-V core.
Privilege architecture is used to provide protection between the different components of the software stack, and try to execute the current operating mode does not allow the authority will cause an exception. RISC-V privileged architecture covers all aspects of the RISC-V systems other than the non-privileged ISA, including privileged instructions, and operating system and other functions required to connect an external device. Each level has a set of core rights of privilege ISA expansion, with optional extensions and variants, including machine ISA, ISA director and management procedures ISA.
The open source is a RISC-V command formal specification code set architecture implementation (executable), written in pure F #, according to reports, the project uses extreme base of F # implementation, this could make do not understand F # does not intend to learn F # of readers You can read and use the specification to achieve.
The implementation is still evolving, the current status and characteristics are as follows:
- It supports the following features
- Basic instruction set: RV32I
- Characteristics Development
- Basic instruction set: RV64I
- Standard Extension M (integer multiply / divide)
- Standard Extension A (atomic memory operation)
- Standard Extended C (16 streamlined instruction)
- Standard Extension F (single precision floating point)
- Standard extension D (double precision floating point)
- Privilege level M (Machine)
- Privileged U (User)
- Privilege level S (Supervisor)
- Virtual memory scheme SV32, SV39 and SV48
- You can apply as have CLI (Command Line Interface) F # supports the flexible implementation of the program and execute RISC-V ELF binaries. This is a sequential explanation: once an instruction sequence memory model.
- We are developed RISC-V test:
- Basic instruction stream
rv32ui-p-*, rv64ui-p-*(Basic set of instructions)rv32um-p-*, rv64um-p-*(M Extended)rv32ua-p-*, rv64ua-p-*(A extension)rv32uc-p-*, rv64uc-p-*(C extensions)
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