m FPGA implementation of baseband data frame frequency offset estimation and compensation based on uw pilot sequence and cordic algorithm, including testbench - Code World

m FPGA implementation of baseband data frame frequency offset estimation and compensation based on uw pilot sequence and cordic algorithm, including testbench

Language 2023-09-06 19:09:17 views: null

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Origin blog.csdn.net/hlayumi1234567/article/details/132726099

m FPGA implementation of baseband data frame frequency offset estimation and compensation based on uw pilot sequence and cordic algorithm, including testbench

m FPGA implementation of QPSK baseband signal frequency offset estimation and compensation algorithm based on FFT Fourier transform, including testbench and matlab constellation diagram display

FPGA implementation of 16QAM baseband signal frequency offset estimation and compensation algorithm based on FFT Fourier transform, including testbench and matlab constellation diagram display

FPGA implementation of 64QAM baseband signal frequency offset estimation and compensation algorithm based on FFT Fourier transform, including testbench and matlab constellation diagram display

m FPGA implementation of 256QAM baseband signal frequency offset estimation and compensation based on FFT Fourier transform, including testbench and matlab constellation display

m Data frame detection based on UW sequence, frame synchronization verilog implementation, including testbench

m Verilog implementation of data frame detection based on double UW sequence, including testbench

m FPGA-based implementation of phase estimation and compensation algorithm for QPSK modulated signal with phase deviation in verilog, including testbench

m FPGA-based verilog implementation of phase estimation and compensation algorithm for 64QAM modulated signal with phase deviation, including testbench

m Data frame detection based on PN sequence, frame synchronization verilog implementation, including testbench

m Data frame detection based on double PN sequence, frame synchronization verilog implementation, including testbench

m FPGA-based implementation of costas ring carrier synchronization verilog, including testbench, which can modify the frequency offset

m FPGA-based Gaussian white noise channel simulation system verilog implementation, including testbench, can be configured with different SNR and frequency offset

m FPGA-based communication data frame scrambling and descrambling verilog implementation, including testbench

m FPGA-based LDPC minimum sum decoding algorithm verilog implementation, including testbench and matlab auxiliary verification program

m FPGA-based data serial-to-parallel conversion system verilog implementation, including testbench, can configure the number of parallel

m FPGA-based FOC controller verilog implementation, including CLARK, PARK, PID and SVPWM, including testbench

m FPGA-based basic OFDM modulation and demodulation verilog implementation, including IFFT and FFT, including testbench

m Verilog implementation of FPGA-based BPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m Verilog implementation of FPGA-based QPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m FPGA-based AGC adaptive gain control system verilog implementation, including testbench

m FPGA-based CRC cyclic redundancy check system verilog implementation, including testbench

m Verilog implementation of FPGA-based interleaving and deinterleaving system, including testbench

m Verilog implementation of FPGA-based DQPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m FPGA-based 256QAM modulation signal generation module verilog implementation, including testbench

m FPGA-based 1024QAM modulation signal generation module verilog implementation, including testbench

m FPGA-based QPSK soft demodulation verilog implementation, including testbench and MATLAB auxiliary verification program

m FPGA-based 16QAM soft demodulation verilog implementation, including testbench

m FPGA-based 8ASK modem system verilog implementation, including testbench test files

m FPGA-based 8PSK modulation and demodulation system verilog implementation, including testbench test files

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