Lorenz chaos system verilog development based on FPGA, including testbench and matlab auxiliary test programs - Code World

Lorenz chaos system verilog development based on FPGA, including testbench and matlab auxiliary test programs

Enterprise 2023-09-09 07:10:04 views: null

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Origin blog.csdn.net/aycd1234/article/details/132510967

Lorenz chaos system verilog development based on FPGA, including testbench and matlab auxiliary test programs

[Lorenz Chaos] Verilog Implementation of Lorenz Chaos System Based on FPGA

m FPGA-based QPSK soft demodulation verilog implementation, including testbench and MATLAB auxiliary verification program

m Implementation of PAPR reduction technology in FPGA-based OFDM system, including testbench test files and MATLAB auxiliary testing

m FPGA-based LDPC minimum sum decoding algorithm verilog implementation, including testbench and matlab auxiliary verification program

m FPGA-based 8FSK modem system verilog implementation, including testbench test files

m FPGA-based 4FSK modem system verilog implementation, including testbench test files

m FPGA-based 8ASK modem system verilog implementation, including testbench test files

m FPGA-based 8PSK modulation and demodulation system verilog implementation, including testbench test files

m FPGA-based 4ASK modem system verilog implementation, including testbench test files

m Verilog implementation of FPGA-based BPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m Verilog implementation of FPGA-based QPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m FPGA-based AGC adaptive gain control system verilog implementation, including testbench

m FPGA-based CRC cyclic redundancy check system verilog implementation, including testbench

m Verilog implementation of FPGA-based interleaving and deinterleaving system, including testbench

m Verilog implementation of FPGA-based DQPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m FPGA-based OFDM modulation and demodulation system verilog implementation, including IFFT, FFT and shaping filters, including testbench

m FPGA-based OFDM system verilog implementation, including IFFT, FFT, shaping filtering and CP addition and CP removal, including testbench

m FPGA-based data serial-to-parallel conversion system verilog implementation, including testbench, can configure the number of parallel

m FPGA-based Gaussian white noise channel simulation system verilog implementation, including testbench, can be configured with different SNR and frequency offset

m FPGA-based FOC controller verilog implementation, including CLARK, PARK, PID and SVPWM, including testbench

m FPGA-based basic OFDM modulation and demodulation verilog implementation, including IFFT and FFT, including testbench

m FPGA-based communication data frame scrambling and descrambling verilog implementation, including testbench

m FPGA-based 256QAM modulation signal generation module verilog implementation, including testbench

m FPGA-based 1024QAM modulation signal generation module verilog implementation, including testbench

m FPGA-based 16QAM soft demodulation verilog implementation, including testbench

FPGA-based image median filter development, including tb test files and matlab verification code

Development of image sobel edge extraction algorithm based on FPGA, including tb test files and matlab verification code

m FPGA-based implementation of phase estimation and compensation algorithm for QPSK modulated signal with phase deviation in verilog, including testbench

m FPGA-based verilog implementation of phase estimation and compensation algorithm for 64QAM modulated signal with phase deviation, including testbench

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