FPGA high-end project: UltraScale GTH + SDI video codec, SDI to SFP optical port loopback output, providing 2 sets of engineering source code and technical support - Code World

FPGA high-end project: UltraScale GTH + SDI video codec, SDI to SFP optical port loopback output, providing 2 sets of engineering source code and technical support

Enterprise 2023-12-16 21:03:42 views: null

NoSuchKey

Guess you like

Origin blog.csdn.net/qq_41667729/article/details/134918026

FPGA high-end project: UltraScale GTH + SDI video codec, SDI to SFP optical port loopback output, providing 2 sets of engineering source code and technical support

FPGA high-end project: UltraScale GTH + SDI video codec, SDI bufferless loopback output, 2 sets of engineering source code and technical support provided

FPGA high-end project: UltraScale GTH + SDI video codec, SDI cache DDR4 loopback output, 2 sets of engineering source code and technical support provided

FPGA high-end project: 6G-SDI video codec, providing engineering source code and technical support

FPGA high-end project: image acquisition + UltraScale GTH + PCIE, aurora 8b/10b codec + PCIE video transmission, providing engineering source code and QT host computer source code and technical support

FPGA high-end project: 4K HDMI video transceiver routine based on GTH, providing engineering source code and technical support

FPGA high-end project: image acquisition + UltraScale GTY + PCIE, aurora 8b/10b codec + PCIE video transmission, providing engineering source code and QT host computer source code and technical support

FPGA GTH aurora 8b/10b codec PCIE board-to-board video transmission, providing 2 sets of engineering source code plus QT host computer source code and technical support

FPGA UltraScale GTH has the most detailed explanation on the entire network, aurora 8b/10b codec, board-to-board video transmission, and provides 2 sets of engineering source code and technical support

FPGA GTH aurora 8b/10b codec PCIE video transmission, provide 2 sets of engineering source code plus QT host computer source code and technical support

FPGA UltraScale GTY has the most detailed explanation on the entire network, aurora 8b/10b codec, HDMI video transmission, providing vivado project source code and technical support

FPGA realizes SDI video transmission and reception based on GS2971/GS2972 Provide engineering source code and technical support

FPGA GTX aurora 8b/10b codec PCIE board-to-board video transmission, providing 2 sets of engineering source code plus QT host computer source code and technical support

FPGA UltraScale GTY has the most detailed explanation on the entire network, aurora 8b/10b codec, board-to-board video transmission, and provides 2 sets of engineering source code and technical support

FPGA pure verilog realizes UDP protocol stack, sgmii interface SFP optical port transceiver, provides engineering source code and technical support

Xilinx Zynq-7000 series FPGA implements video splicing display, providing two sets of engineering source code and technical support

Domestic Gowin FPGA: pure verilog realizes video image scaling, providing 6 sets of Gowin engineering source code and technical support

The most detailed explanation of the whole network of FPGA GTX, aurora 8b/10b protocol, HDMI video transmission, providing 2 sets of engineering source code and technical support

FPGA GTX aurora 8b/10b codec PCIE video transmission, provide 2 sets of engineering source code plus QT host computer source code and technical support

Zynq implements SDI video decoding and PCIE transmission Provides engineering source code and QT host computer source code plus technical support

FPGA realizes 10G UDP communication based on SFP optical port, 10G Ethernet Subsystem replaces network PHY chip, provides engineering source code and technical support

FPGA pure verilog realizes 8-channel video splicing display, providing engineering source code and technical support

FPGA pure verilog realizes 16-channel video splicing display, providing engineering source code and technical support

Xilinx Artix7-100T low-end FPGA decodes MIPI video, implemented based on MIPI CSI-2 RX Subsystem architecture, providing engineering source code and technical support

The most detailed explanation of the whole network of FPGA GTP, aurora 8b/10b protocol, HDMI board-to-board video transmission, providing 2 sets of 4 sets of engineering source code and technical support

The most detailed explanation of the whole network of FPGA GTP, aurora 8b/10b protocol, OV5640 camera board-to-board video transmission, providing 2 sets of 4 sets of engineering source code and technical support

Zynq UltraScale+ XCZU3EG pure VHDL decodes IMX214 MIPI video, 2-channel video splicing output, provides vivado engineering source code and technical support

The most detailed explanation of the whole network of FPGA GTX, aurora 8b/10b protocol, OV5640 board-to-board video transmission, providing 2 sets of engineering source code and technical support

FPGA UltraScale GTH The most detailed explanation on the entire network, aurora 8b/10b codec, HDMI video transmission, 2 sets of engineering source code and technical support provided

Zynq UltraScale+ XCZU3EG decodes MIPI video DP output, MIPI CSI-2 RX Subsystem, provides vivado project source code and technical support

Recommended

Ranking

go common records

SVN power failure recovery

深入理解Redis集群主从复制原理

【二叉树】左叶子之和

[1] The first basic syntax Detailed Kotlin

Linux Ansible creates tasks and executes them

vmware ubuntu virtual machine boots online courses

Use Nodejs to crawl certain data from the web page and write the crawled data into excel (see the next article for the front-end part and the server-side part)

Principle underlying thread pool

The number of bytes occupied when char[ ] is initialized

Daily

More

2025-03-22(0)

2025-03-21(0)

2025-03-20(0)

2025-03-19(0)

2025-03-18(0)

2025-03-17(0)

2025-03-16(0)

2025-03-15(0)

2025-03-14(0)

2025-03-13(0)