Preface:
[Related textbook "Digital Design Principles and Practice (Fourth Edition)"]
This course is a course I fear most. The job will not write, do not experimental, unexamined class ...... the reason causing this result, perhaps because the original did not properly follow the teacher in the class, and lower class not willing to spend the time to learn the reasons, it is a delayed, this will lead to disastrous consequences. But fortunately, everything has the opportunity to remedy, " Wu of the past is not the bridge, and to those who know it can be traced. "
It is in this guilt and remorse, open the "preview" of the road several electricity it ...
Exercises Detailed Chapter III:
(The author is the ultimate goal, of course exam friends, so start with the fastest way is to start from the exercise, step by step back trace knowledge, thereby strengthening memory, another skilled combat skills: The following resolution is only the author of some of his thinking for answers some may not be correct, it has to critical reading, do not blindly believe)
3.7 2-input NAND gate CMOS circuits the number of transistors used for each type of use How many?
Analysis: want to answer this question, we must first of CMOS have some knowledge of basic transistor structure logic gates.
NMOS transistor is used as the pull-down circuit connected to ground, a high input power is turned on
PMOS pull-up transistor is used as the circuit connected to the power supply, the input power source is turned low
The simplest is a CMOS inverter by a NMOS transistor and a PMOS constituting transistors.
NAND gate: in CMOS-based inverters, CMOS NAND gate circuit configuration as the FIG. FIG. It consists of two composed of PMOS transistors and two NMOS transistors , load cell PMOS transistor Q2 and Q4 connected in parallel, the drive tube NMOS transistors Q1 and Q3 connected in series.
( This problem is solved channel may also be extended whereby the NOR gate memory string and a [lower], AND gates, OR gates, etc. )
3.10 gives the "fan-in" and "fan-out" is defined, which one of them is required to be calculated?
Analysis: definition of strategy, fanout must be calculated. (The specific reason I asked some students, more likely explanation is a fan-made devices on the fan-out count has been considered a good help ...... specific reasons to be questionable)
Here To fan-in and fan-out have a certain understanding:
Fanout: logic gate means under conditions which do not exceed the worst-case load specifications, the drive number can be input.
It depends not only on the characteristics of the output terminal, but also on the characteristics of the input of the drive
We must consider two possible outputs: a high state and a low state.
Fanout value = maximum output current / maximum input current.
Total fanout: a high state and the low state fanout fanout smaller value.
3.11 circuits is shown below with one type of NOR gate, draw the menu of the circuit, and with the door or gate or inverter symbols draw the corresponding logic diagram .
Analysis: This question is relatively simple, just for PMOS transistors and CMOS have a certain understanding to the basic functions of the transistor.
A total . 4 inputs, thus a total of 16 cases. One by one analysis just fine.
I figure the red and blue give two examples of the pen ( 0 indicates a low level and non-conductive, an opposite)
3.20 Table 3-3 in the data table to determine the minimum and maximum 74HC00 DC noise margin under the worst conditions. To explain all the assumptions required to answer.
Analysis: [ difficulty of solving the problem is to be understood that the meaning of the subject, and to find the corresponding information in the table. ]
DC noise margin: a measure of the noise level, it indicates how much the output voltage noise is the worst cause damage, a value can not be identified in the input terminal. (In V )
Is generally calculated: V (ILmax of) -V (OLmax) low state DC noise margin; V (OHmin) -V (IHmin) high state DC noise margin
(This method is in fact not difficult to memory, to find the data in the table to four: the maximum value of the minimum high level is input, the input low maximum, minimum output high level, output low level )
Answer this question:
The worst case, the low state DC noise margin: 1.35-0.33 = 1.02V
DC high state noise margin: 3.84-3.15 = 0.69V
Assumed: low state: Vcc = Min = 4mA the IOL high state the VIN = VIH: Vcc = Min IOH = -4mA VIN = VIL
3.22、(？)在3.5节中定义了CMOS电路的7个不同电气参数。用3-3的数据表，确定74HC00的这些参数的最坏值。要说明答案所需的所有假设。
解析：该题首先要知道CMOS电路的7个不同的电气参数分别是什么。
输入高电平VIH和输入低电平VIL
输出高电平VOH和输出高电平VOL
直流噪声容限VNH和VNL
高电平输入电流和低电平输入电流
高电平输出电流和低电平输出电流
(以上是静态特征，找到了10个,其实7个就好了，电流只用算max)
本题解答：
VOHmin CMOS 负载：4.4V TTL 负载：3.84V 假设：Vcc=Min VIN=VIL IOH 为 max VIHmin 3.15V
VOLmax CMOS 负载：0.1V TTL 负载：0.33V 假设：Vcc=Min VIN=VIH IOL 为 max VILmax 1.35V
IOLmax CMOS 负载：20uA TTL 负载：4mA IOHmax CMOS 负载：-20uA TTL 负载：-4mA
IImax 1uA 假设：Vcc=Max VI=0(此时-1uA)或 Vcc(此时 1uA)
(注：这部分的解答有点迷，不太清楚怎么分辨CMOS和TTL，不清楚如何找假设条件)
3.31 何时与朋友握手是重要的？
解析：将 CMOS 器件交给别人时，尤其是在干燥的冬季
3.32 命名CMOS逻辑门延迟的两个分量，哪个受负载电容的影响更大？
解析：转换时间和传播延迟。转换时间受负载电容影响更大。
影响转换时间的因素：(1)晶体管的导通电阻 (2)负载电容[负载电容是指晶振的两条引线连接IC块内部及外部所有有效电容之和，可看作晶振片在电路中串接电容。]
只驱动CMOS输入时，直流负载可忽略。
交流负载决定了输出状态转换时的电压和电流，以及从一个状态转换到另一个状态所需的时间。
3.36 74VHC CMOS器件可在2.5V电源下工作，与工作于5.0V电源的情况相比，这样可以节约多少功耗？
解析：这是一个计算题，知道如何计算功耗即可。
关于功耗：静态状态下CMOS器件的功耗很低。
动态功耗：(1)CMOS输出结构的部分短路，输入电压不接近于供电轨道时，PMOS和NMOS部分导通；功耗取决于VCC的值和输出状态的转换发生率。
PT=C(PD)×VCC^2×f C(PD)：功耗电容 f：输出信号转换的频率
(2)对负载电容CL充放电导致的功耗PL=CL×VCC^2×f CL：负载电容 f：输出信号转换的频率
综上：动态功耗：PD=PT+PL=CPD×VCC^2×f+CL×VCC^2×f=(CPD+CL) × VCC^2×f
本题解答：
PD=PT+PL=(CPD+CL)*VCC^2*f，动态功耗变为 5V 情况下的 1/4
3.37 一个施密特触发反相器，Vilmax=0.8V Vihmin=3.0V Vt+=1.7V Vt-=1.2V，那么它滞后多少？
解析：计算题，要知道如何计算滞后。
Vt+表示正向输入变化的阈值电压 Vt-表示负向输入变化的阈值电压
滞后就是两者的差值
本题解答：t=Vt+-Vt-=1.7V-1.2V=0.5V
3.60 设计一个功能如图的CMOS电路(提示：只需要8个晶体管)
解析：先设计一个非门（两个电子管），然后设计一个或门（六个电子管），最后设计与非门（四个电子管）...这是一个比较麻烦的做法.
助教的完美做法：先考虑设计出“非”门。然后，考虑要求“非”门输出高电位时 B C 均为低电位才能获取高电位；“非”门输出低电位时 B C 任意输入均可得到高电位。根据两条路线设计剩余部分。
3.68 分析图 3-37 中 CMOS 反相器输出下降时间，Rl=900Ω Vl=2.0V。将结果与 3.6.1 节结果比较并解释之
解析:根据三要素分析法
初态：Vh=49/11V 终态：Vl=0.2V 转换后等效电阻 90Ω 时间常数 RC=9ns
输出电压随时间变化关系：Vout=Vl+(Vh-Vl)e^(-t/RC)
将 3.5V 和 1.5V 分别带入求解，得到下降时间 t=ln((3.5-0.2)/(1.5-0.2))*9ns≈8.4ns
与 3.6.1 得到结果相近。因为影响结果的只有 Vl，而 Vl 很小。
(这道题我看了半天都不知道Vh从何而来，如何计算等效电阻？RC要怎么计算？)
[补充一些相关知识：（1）关于CMOS器件的输出下降时间和上升时间的计算。
首先，要明白电容两端的电压不能瞬间改变。因此，即使电路输入的高低电平瞬间改变，对应的等效电阻也瞬间改变，但是电容两边的电压是要有一定延迟的。而这个变化时间是可以计算出来的。具体公式为
，此为下降时间。
,此为上升时间。两处所取的RC均为10nm]
3.79 考虑一个 CMOS8位二进制计数器，时钟频率 16MHz。为计算计数器动态功耗，最低有效位转换频率多少？最高有效位转换频率多少？为计算 8 个输出位动态功耗，应采用什么频率？
解析：时钟频率时指每个单位时间内产生的脉冲的数量，最低位共有两种形态0和1，因此转换频率为时钟频率/2。每上升一位，转换频率便除以2，因此最高位为最低位/2^7。为计算8个输出位的动态功耗，应该取所有位上的频率的平均值。
标准解答：最低有效位转换频率：16MHz/2=8MHz
最高有效位转换频率：8MHz/2^7=8MHz/128=0.0625MHz
应采用频率：求平均值，8MHz*(2-1/2^7)/8≈1.99MHz