Want to see the simulation waveform under the combined.
twf_aes128
timing simulation run over a long time.
[Reserved] vivado of several simulation options and functional simulation, before simulation, post-simulation, timing simulation
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run behavioral simulation
run post-synthesis simulation
run post-synthesis timing simulation
run post-implementation function simulation
run post-implementation timing simulation
Run behavioral simulation
run comprehensive post-simulation
timing simulation run after comprehensive
functional simulation run after the realization
after realization timing simulation run
RTL ANALYSIS: RTL analysis;
Elaboration: Detailed description of the FPGA technology to optimize RTL
Open Elaboration Design：
(1): report methodology: Run design method checks to discover the current design errors
(2): report DRC run design rule checking, and report test results
(3): Report Noise: XDC-based file, check SSO (simultaneous switching output)
Integrated (SYNTHESIS): convert RTL-level design description to a gate-level description, the logic optimization in the process and maps to the primitive Xilinx devices (technology mapping), the device refers to those primitive gate level primitives
SYNTHESIS Settings: Comprehensive parameter options
RTL-level simulation behavior: functional simulation
Integrated back door level simulation: Before simulation, the output of a standard netlist file, the output verilog / VHDL netlist
Timing Simulation: After the simulation, timing simulation model to provide a design after layout
Design Implementation and Analysis (Implentation), for converting the logical and physical design, Implentation setting: parameter setting process implemented
From top to bottom of each FPGA abstraction model system as follows: System level (System) --- >> algorithm level (Alogrithem) ---- >> register transfer level (RTL) ---- >> logic stage (Logic) --- >> stage gate (gate) --- >> circuit switching stages (switch)
Do specific modules at different levels methods used in the design are different, often write some behavioral modules at a high level to be verified by simulation, and its main purpose is to target allocation overall consideration of system performance and each module is not specific circuit implementation.
Comprehensive and thus often do not need to be the next steps. When designing the behavior of the underlying levels closer description often needed to implement circuit logic, when the modules need only be verified through simulations, the need for comprehensive, optimized routing and post-simulation. DETAILED short circuit is gradually upwardly from the bottom. EDA tools are often not only support the HDL description also support schematic entry, effective use of these two methods, one is to improve the efficiency of the design approach.
The following flowchart illustrates schematically the process of compiling and testing modules:
[Reserved] comparison of several emulation mode vivado
https://blog.csdn.net/msrgr/article/details/84143642
1, the Simulation RUN Behavioral behavioral simulation, is often said that functional simulation
2, features the comprehensive post-synthesis function simulation simulation
3, post-synthesis simulation with timing information timing simulation after synthesis, timing and real run on far off
4, a wiring function after post-implementation function simulation simulation
5, timing simulation after post-implementation timing simulation (simulation of the layout) closest to the real execution timing waveform
Distinguish between different emulation mode
Digital circuit design generally includes three major stages: the input source code, and realize comprehensive, and the circuit simulation comes basically consistent with these stages, depending on the applicable simulation can be divided into RTL design stage behavioral simulation, functional simulation and timing simulation integrated back door level. This model not only for the simulation profile FPGA / CPLD design, for the same IC design.
1, RTL behavioral level simulation
在大部分设计中执行的第一个仿真将是RTL行为级仿真。这个阶段的仿真可以用来检查代码中的语法错误以及代码行为的正确性，其中不包括延时信息。如果没有实例化一些与器件相关的特殊底层元件的话，这个阶段的仿真也可以做到与器件无关。因此在设计的初期阶段不使用特殊底层元件即可以提高代码的可读性、可维护性，又可以提高仿真效率，且容易被重用。（绝大部分设计人员将这个阶段的仿真叫功能仿真！）2, integrated back door level functional simulation (pre-simulation)
有门延时。
一般在设计流程中的第二个仿真是综合后门级功能仿真。绝大多数的综合工具除了可以输出一个标准网表文件以外，还可以输出Verilog或者VHDL网表，其中标准网表文件是用来在各个工具之间传递设计数据的，并不能用来做仿真使用，而输出的Verilog或者VHDL网表可以用来仿真，之所以叫门级仿真是因为综合工具给出的仿真网表已经是与生产厂家的器件的底层元件模型对应起来了，所以为了进行综合后仿真必须在仿真过程中加入厂家的器件库，对仿真器进行一些必要的配置，不然仿真器并不认识其中的底层元件，无法进行仿真。Xilinx公司的集成开发环境ISE中并不支持综合后仿真，而是使用映射前门级仿真代替，对于Xilinx开发环境来说，这两个仿真之间差异很小。3, timing simulation (after simulation)
在设计流程中的最后一个仿真是时序仿真。在设计布局布线完成以后可以提供一个时序仿真模型，这种模型中也包括了器件的一些信息，同时还会提供一个SDF时序标注文件（Standard Delay format Timing Anotation）。SDF时序标注最初使用在Verilog语言的设计中，现在VHDL语言的设计中也引用了这个概念。对于一般的设计者来说并不需知道SDFto sum up
行为级仿真时必须的，能够确保你所设计功能是正确的，综合后功能仿真是有必要的，能够排除大部分的时序问题，至于后仿真，只能是解决疑难杂症时再采取的大招，非常费时间，一般不建议做后仿真。Reprinted http://www.openhw.org/topic-1535
vivado Post-Synthesis Simulation
You can simulate a synthesized netlist to verify that the synthesized design meets the functional requirements and behaves as expected. Although it is not typical, you can perform timing simulation with estimated timing numbers at this simulation point.
The functional simulation netlist is a hierarchical, folded netlist expanded to the primitive
module and entity level; the lowest level of hierarchy consists of primitives and macro
primitives.
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