Description of the three-state gate used in FPGA bidirectional IO
In FPGA design, bidirectional IO (input and output pins) is a more troublesome thing, but the inout type is used when the signal line is used for bidirectional data transmission such as a bus.
The following data line with liquid crystal is used as an example of bidirectional IO:
It is said that it is a bidirectional IO port. In fact, input and output are not performed at the same time. A control signal out_en is needed to control when the port is output and when it is input.
Then a three-state gate structure circuit needs to be introduced here.
Three-state gate structure
So what is the structure of the three-state gate?
The output structure of the tri-state gate circuit is very different from the output structure of the ordinary gate circuit, because it adds an output control terminal EN in the circuit.
It can be seen from the above figure that in the single-phase three-state gate, when EN=1, it has no effect on the original circuit, and the output of the circuit conforms to all the logical relationships of the original circuit, that is, A can output to B. When EN = 0, all the internal outputs of the circuit and the external will be in a kind of off state.
Therefore, when the FPGA signal line has bidirectional IO, there can be two three-state gates to control, one control output, one control input, the structure is as follows:
When ENout=1 and ENin=0, the circuit transmission direction of the bidirectional tri-state gate is A->B;
when ENout=0, ENin=1, the circuit transmission direction of the bidirectional tri-state gate is B->A;
Model analysis
The following is a simple model to illustrate how the bidirectional IO functions as an input port and an output port respectively. The block diagram is as follows:
Model pin definition
(1) Definition of input port A: When the bidirectional port dinout is used as the output port, we transfer the input data of port A to the module, and let the data come out from the dinout port.
(2) Definition of output port B: When the two-way port dinout is used as the input port, we transfer the input data of the dinout port to the module, and let the data come out from port B.
(3) EN control signal definition: when EN=1, the three-state gate is turned on and dinout is used as an output port. When EN=0, the three-state gate is set to a high impedance state, and dinout is used as an input port.
Code display
After compiling and analyzing, check the logic circuit from the RTL perspective, which conforms to the original model design.
Summary description
(1) Bidirectional IO signals are not allowed to be transmitted inside the FPGA. Only the FPGA can be defined as a bidirectional IO port to the outside. That is, only the signal output on the top layer can be assigned to a high-impedance state.
(2) In the process of structured modeling, one module is modeled for one function. When the port of the internal module is a bidirectional IO port, then according to a bidirectional IO corresponding to one input, one output and one enable control, Replace the output port of the bidirectional IO in the module with the output port, and replace the input port of the bidirectional IO with the input port, lead to the enable signal, and give the high impedance state z assigned in the assign 0 or 1 according to the actual situation to solve the FPGA internal Two-way IO connection problem.