数电实验 可控分频器

数电实验 可控分频器

主程序：

module yyc_3559_4(clk,x,c0,c1,c,cnt0,cnt1);
input clk,x;
output reg c0=0;
output reg c1=0;
output reg c=0;
output reg [16:0]cnt0=17'b0;
output reg [12:0]cnt1=13'b1;

always@(posedge clk)
begin
if(cnt0==17'd7024)   //  50000000/3559/2=7024
	begin
	cnt0<=0;
	c0<=~c0;
	end
else
	begin
	cnt0<=cnt0+1'b1;
	end
end

always@(posedge clk)
begin
if(cnt1==13'd1844)  //  50000000/13559/2=1844
	begin
	cnt1<=0;
	c1<=~c1;
	end
else
	begin
	cnt1<=cnt1+1'b1;
	end
end

always@(posedge clk)
begin
	if(x==0)
	c<=c0;
	else c<=c1;
end
endmodule

用于modelsim的test文件：

`timescale 10ns/1ns
module text_yyc_3559_4;
reg clk,clr,x;
wire [16:0]cnt0;
wire [12:0]cnt1;
wire c0,c1,c;

initial
begin
x=0;
clk=0;
clr=0;
#5
clr=1;
end

always#1 clk=~clk;
always#100000 x=~x;

yyc_3559_4 text(
.clk(clk),
.cnt0(cnt0),
.cnt1(cnt1),
.c0(c0),
.c1(c1),
.c(c),
.x(x)
);
endmodule