声明：这篇博文只是一个大概性的认识，有一篇更走心的博文请看：MMCME2_ADV介绍 高级混合模式时钟管理器（7 Series FPGA）
下面介绍的一个基本锁相环时钟电路是Spartan-6里面的一个设计元件（Design element）：
PLL_BASE
基本锁相环时钟电路（ Basic Phase Locked Loop Clock Circuit）原语。
This design element is a direct sub-set of the PLL_ADV design element, an embedded Phase Locked Loop clock circuit that provides added capabilities for clock synthesis and management both within the FPGA and in circuits external to the FPGA. The PLL_BASE is provided in order to ease the integration for most PLL clocking circuits. However, this primitive does not contain all of the functionality that the PLL can possibly provide. This component allows the input clock to be phase shifted, multiplied and divided, and supports other features, such as modification of the duty cycle and jitter filtering.
该设计元素是PLL_ADV设计元素的直接子集，嵌入式锁相环时钟电路，为FPGA内部和FPGA外部电路提供时钟合成和管理的附加功能。 提供PLL_BASE是为了简化大多数PLL时钟电路的集成。 但是，该原语不包含PLL可能提供的所有功能。 该组件允许输入时钟进行相移，乘法和除法，并支持其他功能，例如修改占空比和抖动滤波。
端口介绍：
需要解释的是：CLKFBOUT这个端口，根据上面的描述：
Dedicated PLL feedback output used to determine how the PLL compensates clock network delay.
Depending on the type of compensation desired, this output might or might not need to be connected.
专用PLL反馈输出用于确定PLL如何补偿时钟网络延迟。
根据所需的补偿类型，可能需要或可能不需要连接此输出。
可知这是一个反馈输出端，与之相对应的是：CLKFBIN，应该是反馈输入端：
Clock feedback input. This pin should only be sourced from the CLKFBOUT port.
时钟反馈输入。 该引脚应仅来自CLKFBOUT端口。
Design Entry Method
从上面的表格来看，需要用户例化来使用。
可用参数介绍（Available Attributes）：
下面一一解释
COMPENSATION：默认值为"SYSTEM_SYNCHRONOUS"。
Specifies the PLL phase compensation for the incoming clock.
SYSTEM_SYNCHRONOUS attempts to compensate all clock delay while SOURCE_SYNCHRONOUS is used when a clock is provided with data and thus phased with the clock.
指定输入时钟的PLL相位补偿。 SYSTEM_SYNCHRONOUS尝试补偿所有时钟延迟，而当时钟被提供数据并因此与时钟定相时，使用SOURCE_SYNCHRONOUS。
BANDWIDTH：默认为 "OPTIMIZED" 。
Specifies the PLL programming algorithm affecting the jitter, phase margin and other characteristics of the PLL.
指定影响PLL的抖动，相位裕度和其他特性的PLL编程算法。
CLKOUT0_DIVIDE,
CLKOUT1_DIVIDE,
CLKOUT2_DIVIDE,
CLKOUT3_DIVIDE,
CLKOUT4_DIVIDE,
CLKOUT5_DIVIDE
Specifies the amount to divide the associated CLKOUT clock output if a different frequency is desired. This number in combination with the FBCLKOUT_MULT value determines the output frequency.
如果需要不同的频率，则指定分配相关CLKOUT时钟输出的量。 此数字与FBCLKOUT_MULT值组合确定输出频率。
CLKOUT0_PHASE,
CLKOUT1_PHASE,
CLKOUT2_PHASE,
CLKOUT3_PHASE,
CLKOUT4_PHASE,
CLKOUT5_PHASE
Allows specification of the output phase relationship of the associated CLKOUT clock output in number of degrees offset (i.e. 90 indicates a 90 degree or ¼ cycle offset phase offset while 180 indicates a 180 degree offset or ½ cycle phase offset).
允许以度数偏移量指定相关CLKOUT时钟输出的输出相位关系（即，90表示90度或1/4周期偏移相位偏移，而180表示180度偏移或1/2周期相位偏移）。
CLKOUT0_DUTY_CYCLE,
CLKOUT1_DUTY_CYCLE,
CLKOUT2_DUTY_CYCLE,
CLKOUT3_DUTY_CYCLE,
CLKOUT4_DUTY_CYCLE,
CLKOUT5_DUTY_CYCLE,
Specifies the Duty Cycle of the associated CLKOUT clock output in percentage (i.e. 0.50 generates a 50% duty cycle).
以百分比形式指定相关CLKOUT时钟输出的占空比（即0.50产生50％占空比）。
CLKFBOUT_MULT：
Specifies the amount to multiply all CLKOUT clock outputs if a different frequency is desired. This number in combination with the associated CLKOUT#_DIVIDE value determines the output frequency.
指定在需要不同频率时将所有CLKOUT时钟输出相乘的量。 该数字与相关的CLKOUT＃_DIVIDE值组合确定输出频率。
DIVCLK_DIVIDE：
Specifies the division ratio for all output clocks.
指定所有输出时钟的分频比。
CLKFBOUT_PHASE
Specifies the phase offset in degrees of the clock feedback output.
指定时钟反馈输出的相位偏移（以度为单位）。
REF_JITTER
The reference clock jitter is specified in terms of the UI which is a percentage of the reference clock. The number provided should be the maximum peak to peak value on the input clock.
参考时钟抖动是根据UI指定的，UI是参考时钟的百分比。 提供的数字应该是输入时钟的最大峰峰值。
CLKIN_PERIOD
Specified the input period in ns to the PLL CLKIN input.
用ns指定到PLL CLKIN输入的输入周期。
例化模板：
Verilog Instantiation Template
// PLL_BASE: Phase-Lock Loop Clock Circuit
// Virtex-5, Spartan-6
// Xilinx HDL Libraries Guide, version 11.2
PLL_BASE #(
.BANDWIDTH("OPTIMIZED"), // "HIGH", "LOW" or "OPTIMIZED"
.CLKFBOUT_MULT(1), // Multiplication factor for all output clocks
.CLKFBOUT_PHASE(0.0), // Phase shift (degrees) of all output clocks
.CLKIN_PERIOD(0.000), // Clock period (ns) of input clock on CLKIN
.CLKOUT0_DIVIDE(1), // Division factor for CLKOUT0 (1 to 128)
.CLKOUT0_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT0 (0.01 to 0.99)
.CLKOUT0_PHASE(0.0), // Phase shift (degrees) for CLKOUT0 (0.0 to 360.0)
.CLKOUT1_DIVIDE(1), // Division factor for CLKOUT1 (1 to 128)
.CLKOUT1_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT1 (0.01 to 0.99)
.CLKOUT1_PHASE(0.0), // Phase shift (degrees) for CLKOUT1 (0.0 to 360.0)
.CLKOUT2_DIVIDE(1), // Division factor for CLKOUT2 (1 to 128)
.CLKOUT2_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT2 (0.01 to 0.99)
.CLKOUT2_PHASE(0.0), // Phase shift (degrees) for CLKOUT2 (0.0 to 360.0)
.CLKOUT3_DIVIDE(1), // Division factor for CLKOUT3 (1 to 128)
.CLKOUT3_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT3 (0.01 to 0.99)
.CLKOUT3_PHASE(0.0), // Phase shift (degrees) for CLKOUT3 (0.0 to 360.0)
.CLKOUT4_DIVIDE(1), // Division factor for CLKOUT4 (1 to 128)
.CLKOUT4_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT4 (0.01 to 0.99)
.CLKOUT4_PHASE(0.0), // Phase shift (degrees) for CLKOUT4 (0.0 to 360.0)
.CLKOUT5_DIVIDE(1), // Division factor for CLKOUT5 (1 to 128)
.CLKOUT5_DUTY_CYCLE(0.5), // Duty cycle for CLKOUT5 (0.01 to 0.99)
.CLKOUT5_PHASE(0.0), // Phase shift (degrees) for CLKOUT5 (0.0 to 360.0)
.COMPENSATION("SYSTEM_SYNCHRONOUS"), // "SYSTEM_SYNCHRONOUS",
// "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL",
// "DCM2PLL", "PLL2DCM"
.DIVCLK_DIVIDE(1), // Division factor for all clocks (1 to 52)
.REF_JITTER(0.100) // Input reference jitter (0.000 to 0.999 UI%)
) PLL_BASE_inst (
.CLKFBOUT(CLKFBOUT), // General output feedback signal
.CLKOUT0(CLKOUT0), // One of six general clock output signals
.CLKOUT1(CLKOUT1), // One of six general clock output signals
.CLKOUT2(CLKOUT2), // One of six general clock output signals
.CLKOUT3(CLKOUT3), // One of six general clock output signals
.CLKOUT4(CLKOUT4), // One of six general clock output signals
.CLKOUT5(CLKOUT5), // One of six general clock output signals
.LOCKED(LOCKED), // Active high PLL lock signal
.CLKFBIN(CLKFBIN), // Clock feedback input
.CLKIN(CLKIN), // Clock input
.RST(RST) // Asynchronous PLL reset
);
// End of PLL_BASE_inst instantiation