Vivado XDC Bunken

 

Foreword

You can refer to the "Xilinx FPGA authoritative design guidelines", as well as the manual provided by Xilinx, as shown below. References Cited in the article is good, it is worth reading.

1, UCF / XDC Common Commands

UCF constraint mapping relationship between XDC command

UCF	XDC	effect
TIMESPEC PERIOD	create_clock create_generated_clock
OFFSET= IN<x>BEFORE<clk>	set_input_delay
OFFSET=OUT<x>BEFORE<clk>	set_output_delay
FROM:TO "TS_" *2	set_multicycle_path
FROM:TO	set_max_delay
TIG	set_false_path
NET "clk_p" LOCK = AD12	set_property LOC AD12 [get_ports clk_p]	The signal port clk_p bound with FPAG chip pin AD12.
NET "clk_p" IOSTANDARD=LVDS	set_property IOSTANDART LVDS [get_ports clk_p]	The level of the standard signal port clk_p set to LVDS.

 

Common
set	expr	list	filter
current_instance	get_hierarchy_separator	set_hierarchy_separator	get_property
set_property	set_units	endgroup	start group
Timing Constraints
create_clock	create_generated_clock	group_path	set_clock_groups
set_clock_latency	set_data_check	set_disable_timing	set_false_path
set_input_delay	set_output_delay	set_max_delay	set_min_delay
set_multicycle_path	set_case_analysis	set_clock_sense	set_clock_uncertainty
set_input_jitter	set_max_time_borow	set_propagated_clock	set_system_jitter
set_external_delay
Physical constraints
add_cells_to_pblock	create_pblock	delete_pblock	remove_cells_from_pblock
resize_pblock	create_macro	delete_macros	update_macro

 

 

2, pin constraint

(1) I / O pin assignment set syntax

set_property PACKAGE_PIN <pin name>[get_port <port>    ] ##规范
set_property PACKAGE_PIN W13       [get_port light_led1] ##举例

(2) IO pins are driving the ability to set syntax

set_property DRIVE<2 4 6 8 12 16 24>[get_ports<ports>]

(3) IO pin electrical set the standard syntax

set_property IOSTANDARD <IO standard> [get_ports <ports>   ]  ##规范
set_property IOSTANDARD LVCMOS33      [get_ports light_led2]  ##举例

(4) IO pins dither setting syntax

set_property SLEW <SLOW|FAST>[get_ports<ports>]

Pull Set syntax on (5) IO pins

set_property PULLUP true[get_ports<ports>]

(6) set the syntax at IO pins

set_property PULLDOWN true [get_ports<ports>]

references

Author	Blog
1, Longbow insistence	XDC constraints skills --CDC articles
	XDC constraint Skills clock articles
	XDC constraint Skills I / O articles (on)
	XDC constraint Skills I / O articles (under)
2、Times_poem	xdc file acquaintance clock constraints
	Vivado packet clock constraint three applications
3、angelbosj	IO port constraints on vivado