分频器\计数器\led显示

实验平台

硬件：使用Xilinx Artix-7 FPGA芯片，具体型号为XC7A75TFGG484-1。
软件：Vivado 2018.1

实现功能

1）时钟分频器产生1Hz时钟，设计一个10进制计数器。以递减方式工作。
2）除了计数器的功能外，通过板上拨动开关，增加右移和循环右移运行模式，移动速度同计数器的计数频率。
3）通过板上拨动开关，选择计数器可以以递增或递减模式工作，可以实现计数器计数频率的变化

代码

top.v

`timescale 1ns / 1ps

module top( 
	input rst, 
	input clk,//100MHz
	input flag,//counter
	input flag1,//Hz
	input flag2,  //display
	output [7:0] led
);   
wire divclk;  
     divclk U1(.rst1(rst),.flag1(flag1),.clk1(clk),.divclk1(divclk));   
     led U2(.rst2(rst),.divclk2(divclk),.flag(flag),.flag2(flag2),.led8(led)); 
endmodule 

divclk.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/12/07 21:12:09
// Design Name: 
// Module Name: divclk
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module divclk(
	input clk1,//100MHz
	input rst1,//
	input flag1,//
	output reg divclk1//
);
reg[31:0] counter1; 
always @(posedge clk1 or posedge rst1)
begin
if(rst1) 
begin         
  counter1<=0;  
 divclk1<=0;    
 end    
else   
if(flag1==0)
begin
  if(counter1==32'h02faf07f) //1Hz
      begin  
      counter1<=0;
      divclk1<=~divclk1; 
      end    
  else    
      counter1<=counter1+1;   
end

else if(flag1==1)
begin
  if(counter1==32'h04c4b3f) //10Hz
      begin  
      counter1<=0;
      divclk1<=~divclk1; 
      end    
  else    
      counter1<=counter1+1;   
end
end   
endmodule 

led.v

`timescale 1ns / 1ps 

module led( 
	input divclk2, 
	input rst2,
	input flag,//counter
	input flag2, //display
	output reg [7:0] led8    
); 

reg[3:0] counter2;
always@( posedge divclk2 or posedge rst2 )
begin
    if(flag==0)
        begin
        if(rst2)
        counter2<=9;
        else 
            begin
            if(counter2==0)
            counter2<=9; 
            else      
            counter2<=counter2-1;
            end   
        end
    else if(flag==1)
        begin
        if(rst2)
            counter2<=0;
        else 
            begin
            if(counter2==9)
            counter2<=0; 
            else      
            counter2<=counter2+1;
            end
        end   
end

//display
always @*   
  begin
  if(flag2==0)
  begin    
  case(counter2)   
     4'b0000:  led8=8'b00000001;   
     4'b0001:  led8=8'b00000010;    
     4'b0010:  led8=8'b00000100;
     4'b0011:  led8=8'b00001000; 
     4'b0100:  led8=8'b00010000;    
     4'b0101:  led8=8'b00100000;   
     4'b0110:  led8=8'b01000000;   
     4'b0111:  led8=8'b10000000;     
     default:  led8=8'b00000000;         
  endcase
  end
  else if(flag2==1)
  begin
    case(counter2)   
     4'b0000:  led8=8'b00000000;    
     4'b0001:  led8=8'b00000001;    
     4'b0010:  led8=8'b00000010;
     4'b0011:  led8=8'b00000011; 
     4'b0100:  led8=8'b00000100;    
     4'b0101:  led8=8'b00000101;   
     4'b0110:  led8=8'b00000110;   
     4'b0111:  led8=8'b00000111;   
     4'b1000:  led8=8'b00001000;   
     4'b1001:  led8=8'b00001001;         
     default:  led8=8'b11111111;     
  endcase
  end 
  end
endmodule